Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsPMICsPMIC - power management - special purpose 370 µA MAPBGA 130 (8x8)

Document Number: MC34709

Rev. 3.0, 2/2013

Freescale Semiconductor

Advance Information

* This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

Power Management Integrated

Circuit (PMIC) for i.MX50/53

Families

The 34709 is the Power Management Integrated Circuit (PMIC)

designed primarily for use with the Freescale i.MX50 and i.MX53

families. It offers a low cost solution targeting embedded applications

that do not require a battery charger. However, it can be easily

combined with an external charger, allowing flexibility for either single

or multi-cell Li-Ion battery configurations. It supports both consumer

and industrial applications with a single 130-pin 8x8 MAPBGA 0.5

pitch package that is easily routable in low cost board designs.

Features

• Six multi-mode buck regulators for direct supply of the processor

core, memory, and peripherals.

• Boost regulator for USB PHY domain on i.MX processors.

• Eight LDO regulators with internal and external pass devices for

thermal budget optimization and DDR memory voltage reference

• 10-bit ADC for monitoring battery and other inputs

• Real time clock and crystal oscillator circuitry with a coin cell

backup/charger

• SPI/I

C bus for control and register interface

• Four general purpose low-voltage I/Os with interrupt capability

• Two PWM outputs

Figure 1. Simplified Application Diagram

POWER MANAGEMENT

34709

Applications

Tablets

Smart Mobile Devices

Patient Monitors

Digital Signage

Human Machine Interfaces (HMI)

VK SUFFIX (PB-FREE)

98ASA00333D

130 MAPBGA

8.0 X 8.0 (0.5 MM PITCH)

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Summary of content (140 pages)

PAGE 1
Freescale Semiconductor Advance Information Document Number: MC34709 Rev. 3.0, 2/2013 Power Management Integrated Circuit (PMIC) for i.MX50/53 Families 34709 The 34709 is the Power Management Integrated Circuit (PMIC) designed primarily for use with the Freescale i.MX50 and i.MX53 families. It offers a low cost solution targeting embedded applications that do not require a battery charger.
PAGE 2
Table of Contents 1 Orderable Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Part Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . .
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7.9 8 Register Set structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.9.2 Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.9.3 SPI/I2C Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Orderable Parts 1 Orderable Parts This section describes the part numbers available to be purchased, along with their differences. Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to http://www.freescale.com and perform a part number search for the following device numbers. Table 1. Orderable Part Variations Part Number (1) MC34709VK Temperature (TA) -40 to 85 °C Package 130 MAPBGA - 8.0 x 8.0 mm - 0.5 mm Pitch Notes 1.
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Part Identification 2 Part Identification This section provides an explanation of the part numbers and their alpha numeric breakdown. 2.1 Description Part numbers for the chips have fields that identify the specific part configuration. You can use the values of these fields to determine the specific part you have received. 2.
PAGE 6
Internal Block Diagram 3 Internal Block Diagram O/P Drive SW1 Dual Phase GP 2000 mA Buck GNDADC 10 Bit GP ADC ADIN9 A/D Control MUX O/P Drive SW2 LP ` 1000 mA Buck Touch Screen Interface Die Temp & Thermal Warning Detection TSREF To Interrupt Section SW3 INT MEM 500 mA Buck SW4 Dual Phase DDR 1000 mA Buck Package Pin Legend Input Pin CS CLK MOSI MISO GNDSPI Shift Register SPI Interface + Muxed I2C Optional Interface SW5 I/O 1000 mA Buck To Enables & Control Registers VDDLP SW3IN SW3LX G
PAGE 7
Pin Connections 4 Pin Connections 4.
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Pin Connections 4.2 Pin Definitions Table 3. Pin Definitions Pin Number Pin Name Pin Function Definition N1 BP I 1. Application supply point 2.
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Pin Connections Table 3.
PAGE 10
Pin Connections Table 3. Pin Definitions (continued) Pin Number Pin Name Pin Function Definition C8 GPIOVDD I C7 GPIOLV0 I/O General purpose input/output 1 B7 GPIOLV1 I/O General purpose input/output 2 B9 GPIOLV2 I/O General purpose input/output 3 E10 GPIOLV3 I/O General purpose input/output 4 A8 PWM1 O PWM output 1 A7 PWM2 O PWM output 2 C9 GNDGPIO GND GPIO ground Supply for GPIOLV pins Clock/RTC/Coin Cell I 1. Coin cell supply input O 2.
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Pin Connections Table 3.
PAGE 12
General Product Characteristics 5 General Product Characteristics 5.1 Maximum Ratings Table 4. Maximum Ratings All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Symbol Description (Rating) Min. Max. Unit Notes • BP - 4.8 V • LICELL - 4.8 • VCOREREF - 1.5 • VCOREDIG, VDDLP - 1.6 • VCORE - 3.6 • SWxIN, SWxLX, SWBSTFB - 5.5 • SWxFB, SWxPWGD, SWxCFG - 3.6 • SWBSTLX - 7.
PAGE 13
General Product Characteristics 5.2 Thermal Characteristics The thermal rating data of the packages has been simulated with the results listed in Table 5. Table 5. Thermal Ratings Symbol Description (Rating) Min. Max.
PAGE 14
General Product Characteristics 5.2.1 Estimation of Junction Temperature An estimation of the chip junction temperature TJ can be obtained from the equation • TJ = TA + (RθJA x PD) where • TA = Ambient temperature for the package in °C • RJA = Junction to ambient thermal resistance in °C/W • PD = Power dissipation in the package in W The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance.
PAGE 15
General Product Characteristics 5.3 Electrical Characteristics 5.3.1 Recommended Operating Conditions Table 7. Recommended Operating Conditions Symbol Description (Rating) VBP VLICELL TA 5.3.2 Min. Max. Unit Main Input Supply 3.0 4.5 V LICELL Backup Battery 1.8 3.6 V Ambient Temperature -40 85 °C Notes General PMIC Specifications Table 8.
PAGE 16
General Product Characteristics Table 8. Pin Logic Thresholds Pin Name MISO, INT Internal Termination (19) ICTEST SW1CFG, SW4CFG 23. 24. Min Max (22) Unit Notes Output Low -100 A 0.0 0.2 V (15) (24) Output High 100 A SPIVCC - 0.2 SPIVCC V (15) (24) Input Low PUMSxS = 0 - 0.0 0.3 V (17) Input High PUMSxS = 1 - 1.0 VCOREDIG V (17) Input Low - 0.0 0.3 V (18) Input High - 1.1 1.7 V (18) Input Low - 0.0 0.3 V Input Mid - 1.3 2.0 V Input High - 2.5 3.
PAGE 17
General Product Characteristics 5.3.3 Current Consumption Table 9 provides the current consumption for standard use cases. Table 9. Current Consumption Summary (27) Characteristics noted under conditions BP = 3.6 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Mode Description Typ Max Unit 4.0 8.
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General Product Characteristics Table 9. Current Consumption Summary (27) Characteristics noted under conditions BP = 3.6 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
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General Description 6 General Description 6.1 Features Power Generation • Six buck switching regulators • Two single/dual phase buck regulators • Three single phase buck regulators • Up to six independent outputs • PFM/PWM operation mode • Dynamic voltage scaling • Boost regulator • Support for USB physical layer on i.
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General Description 6.2 Block Diagram SIX BUCK REGULATORS Processor Core Split Power Domains DDR Memory I/O EIGHT LDO REGULATORS Peripherals BOOST REGULATOR CONTROL INTERFACE SPI/I2C 34709 BIAS & REFERENCES Trimmed Bandgap 32.768 kHz CRYSTAL OSCILLATOR Real Time Clock SRTC Support Coin Cell charger 10 BIT ADC CORE General Purpose Resistive Touch Screen Interface POWER CONTROL LOGIC State Machine GENERAL PURPOSE I/O & PWM OUTPUTS Figure 4.
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Functional Block Description 7 Functional Block Description 7.1 Start-up Requirements Upon application of power, there is an initial delay of 8.0 ms during which the core circuitry is enabled. Then the switching and linear regulators are sequentially enabled in time slots of 2.0 ms steps. This allows the PMIC to limit the inrush current. The outputs of the switching regulators not enabled, are discharged with weak pull-downs on the output to ensure a proper power-up sequence.
PAGE 22
Functional Block Description Table 10. Power-up Defaults i.MX Reserved 53 LPM 53 DDR2 53 DDR3 53 LVDDR3 53 LVDDR2 50 mDDR 50 50 50 50 50 LPDDR2 LPDDR2 mDDR LPDDR2 mDDR VSRTC Reserved 1.2 1.3 1.3 1.3 1.3 1.2 1.2 1.2 1.2 1.2 1.2 VPLL Reserved 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 VREFDDR Reserved On On On On On On On On On On On VDAC Reserved 2.775 2.775 2.775 2.775 2.775 2.5 2.5 2.5 2.5 2.5 2.5 VGEN1 Reserved 1.2 1.3 1.3 1.3 1.3 1.
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Functional Block Description 7.2 Bias and References Block All regulators use the main bandgap as the reference. The main bandgap is bypassed with a capacitor at VCOREREF. The bandgap and the rest of the core circuitry is supplied from VCORE. The performance of the regulators is directly dependent on the performance of VCORE and the bandgap. No external DC loading is allowed on VCOREDIG or VCOREREF. VCOREDIG is kept powered as long as there is a valid supply and/or coin cell.
PAGE 24
Functional Block Description 7.3 7.3.1 Clocking and Oscillators Clock Generation A system clock is generated for internal digital circuitry as well as for external applications utilizing the clock output pins. A crystal oscillator is used for the 32.768 kHz time base and generation of related derivative clocks. If the crystal oscillator is not running (for example, if the crystal is not present), an internal 32 kHz oscillator will be used instead.
PAGE 25
Functional Block Description Table 14. Oscillator and Clock Main Electrical Specifications Characteristics noted under conditions BP = 3.6 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max 0.0 - 0.2 CLK32KVCC-0.2 VSRTC-0.2 - CLK32KVCC - VSRTC • CLK32KDRV [1:0] = 00 - 6.0 - • CLK32KDRV [1:0] = 01 (default) - 2.5 - • CLK32KDRV [1:0] = 10 - 3.
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Functional Block Description Open Drain output for RTC wake-up Processor SPIVCC=1.8 V I/O Core Supply SOG Supply 34709 GP Domain=1.1 V LP Domain=1.2 V ON Detect PWRONx Best Of Suppy HP-RTC VSRTC = 1.2 V LP-RTC VCOREDIG Vcoredig SRTC 32 kHz for DSM timing 32 kHz CKIL: VSRTC 0.1 µF On/Off Button Vsrtc & Detect CLK32KMCU Main Battery Coin Cell Battery Figure 5. SRTC Block Diagram 7.3.2.1 VSRTC The VSRTC regulator provides the CLK32KMCU output level.
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Functional Block Description Table 15. VSRTC Electrical Specifications Characteristics noted under conditions BP = 3.6 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit 1.15 1.2 1.25 V 1.25 1.3 1.35 V - 0.8 - A - - 1.
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Functional Block Description A clock calibration system is provided to adjust the 32,768 cycle counter that generates the 1.0 Hz timer for RTC timing registers. The general implementation relies on the system processor to measure the 32.768 kHz crystal oscillator against a higher frequency and more accurate system clock, such as a TCXO. If the RTC timer needs a correction, a 5-bit 2’s complement calibration word can be sent via the SPI, to compensate the RTC for inaccuracy in its reference oscillator.
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Functional Block Description If COINCHEN=1 when the system goes into an Off or User Off state, the coin cell charger will continue to charge to the predefined voltage setting, but at a lower maximum current ICOINLO. This compensates for self discharge of the coin cell and ensures that when the main cell gets depleted, the coin cell will be topped off for maximum RTC retention. The coin cell charging will be stopped for the BP below UVDET. The bit COINCHEN itself is only cleared when an RTCPORB occurs.
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Functional Block Description Interrupts generated by external events are debounced, therefore, the event needs to be stable throughout the debounce period before an interrupt is generated. Nominal debounce periods for each event are provided in Table 20. Due to the asynchronous nature of the debounce timer, the effective debounce time can vary slightly. 7.4.2 Interrupt Bit Summary Table 20 summarizes all interrupt, mask, and sense bits associated with INT control.
PAGE 31
Functional Block Description 7.5 Power Generation The 34709 PMIC provides reference and supply voltages for the application processor as well as peripheral device. Six buck (step down) converters and one boost (step up) converters are included. One of the buck regulators can be configured in dual phase, single phase mode, or operate as separate independent outputs (in this case, there are six buck converters).
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Functional Block Description 7.5.2 Modes of Operation The 34709 PMIC is fully programmable via the SPI interface and associated register map. Additional communication is provided by direct logic interfacing including interrupt, watchdog and reset. Default start-up of the device is selectable by hardwiring the Power-up Mode Select (PUMS) pins. Power cycling of the application is driven by the 34709 PMIC.
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Functional Block Description Coin cell BP < UVDET BP > UVDET From Any Mode: Loss of Power with PCEN=0, Thermal Protection Trip, or System Reset PCT[7:0] Expired Off Unqual’d Turn On WDI Low, WDIRESET=0 Unqual’d Turn On Turn On Event Start Up Modes Warm Start Reset Timer Expired Reset Timer Expired Watchdog Cold Start WDI Low, WDIRESET=1 and PCMAXCNT is exceeded WDI Low, WDIRESET=1 and PCMAXCNT not exceeded Watchdog Timer Expired On Turn On Event (Warm Boot) Turn On Event (Warm Start) Proc
PAGE 34
Functional Block Description 7.5.2.1 Coin Cell The RTC module is powered from the coin cell due to insufficient voltage at BP and the PMIC not being in a Power Cut. In this state, no Turn On event is accepted and transitioning to the Off state would requires BP restoration with a threshold above UVDET. RESETB, and RESETBMCU are held low in this mode. The RTC module remains active (32 kHz oscillator + RTC timers), along with BP level detection to qualify exit to the Off state.
PAGE 35
Functional Block Description 7.5.2.7 Memory Hold and User Off (Low-power Off states) As noted in the User Off Wait description, the system is directed into low-power Off states based on a SPI command in response to an intentional turn off by the end user, therefore the only way to exit this mode will be through a turn on event. To the end user, the Memory Hold and User Off states look like the product has been shut down completely.
PAGE 36
Functional Block Description 7.5.2.10 Warm Start Entered upon a Turn On event from User Off. The first 8.0 ms is used for initialization, which includes bias generation, PUMSx latching, and qualification of the BP supply level. The switching and linear regulators are then powered up sequentially to limit the inrush current; see Start-up Requirements for sequencing and default level details.
PAGE 37
Functional Block Description After a successful power-up from a PCUT (i.e., valid power is re-established, the system comes out of reset and the processor re-assumes control), software should clear the PCCOUNT [3:0] counter. Counting of PCUT events is enabled via the PCCOUNTEN bit. This mode is only supported if the power cut mode feature is enabled by setting the PCEN bit. When not enabled, then in case of a power failure, the state machine will transition to the Off mode.
PAGE 38
Functional Block Description Table 22. PWRONx Hardware Debounce Bit Settings(37) Bits PWRONxDBNC[1:0] State Turn On Debounce (ms) Falling Edge INT Debounce (ms) Rising Edge INT Debounce (ms) 00 0.0 31.25 31.25 01 31.25 31.25 31.25 10 125 125 31.25 11 750 750 31.25 Notes 37. The sense bit PWRONxS is not debounced and follows the state of the PWRONx pin. • Battery Attach: This occurs when BP crosses the 3.
PAGE 39
Functional Block Description 7.5.3.6 Timers The different timers as used by the state machine are listed on Table 24; this listing does not include RTC timers for timekeeping. A synchronization error of up to one clock period may occur with respect to the occurrence of an asynchronous event, the duration listed on Table 24 is therefore the effective minimum time period. Table 24. Timer Main Characteristics 7.5.3.6.1 Timer Duration Clock Under-voltage Timer 4.
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Functional Block Description 7.5.3.7 Power Monitoring The voltage at BP is monitored by detectors as summarized in Table 25. Table 25. LOWBATT Detection Thresholds Threshold Voltage (V) Power on 3.0 Low input supply warning 2.9 • BP (H to L)(38) UVDET rising(39) 3.0 UVDET Falling(39) 2.65 Notes 38. 50 mV hysteresis is applied. 39. ± 4.0 % tolerance The UVDET and Power on thresholds are related to the power on/off events as described earlier in this chapter.
PAGE 41
Functional Block Description Table 27. Standby Pin and Polarity Control STANDBY (Pin) STANDBYINV (SPI bit) STANDBY Control(40) 0 0 0 0 1 1 1 0 1 1 1 0 Notes 40. STANDBY = 0: System is not in Standby STANDBY = 1: System is in Standby The state of the STANDBY pin only has influence in On mode, therefore it is ignored during start-up and in the Watchdog phase.
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Functional Block Description Table 29. Buck Operating Modes Mode Description OFF The regulator is switched off and the output voltage is discharged PFM Pulse Frequency Modulation: The regulator is switched on and set to PFM mode operation. In this mode, the regulator is always running in PFM mode. Useful at light loads for optimized efficiency. APS Automatic Pulse Skip: The regulator is switched on and set to Automatic Pulse Skipping.
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Functional Block Description Table 30. Switching regulator Mode Control for Normal and Standby Operation SWxMODE[3:0] Normal Mode Standby Mode 1101 PWM PFM 1110 Reserved Reserved 1111 PFM PFM In addition to controlling the operating mode in Standby, the voltage setting can be changed. The voltage transition slope is controlled by DVS, see Dynamic Voltage Scaling section for details. Each regulator has an associated set of SPI bits for Standby mode set points.
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Functional Block Description The clocking system provides a near instantaneous activation when the switching regulators are enabled or when exiting PFM operation to PWM mode. The PLL can be configured for continuous operation with PLLEN = 1. 7.5.4.3 SW1 SW1 is a fully integrated synchronous buck PWM voltage mode controlled DC/DC regulator. It can be operated in single phase/ dual phase mode. The operating mode of the switching regulator is configured by the SW1CFG pin.
PAGE 45
Functional Block Description BP SW1IN SW1AMODE ISENSE CINSW1A SW1 Controller SW1ALX Driver L SW1A DSW1A COSW1A SW1FAULT GNDSW1A Internal Compensation SW1FB SPI Z2 Z1 EA SPI Interface V REF DAC BP SW1BIN SW1BMODE ISENSE CINSW1B Controller SW1BLX LSW 1B Driver DSW1B COSW 1B GNDSW1B SW1CFG Figure 9. SW1 Dual Phase Output Mode Block Diagram The peak current is sensed internally for over-current protection purposes.
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Functional Block Description Table 35. SW1A/B Output Voltage Programmability Set Point SW1A[5:0] SW1A/B Set Point SW1A[5:0] Output (V) SW1A/B Output (V) 13 001101 0.8125 45 101101 1.2125 14 001110 0.8250 46 101110 1.2250 15 001111 0.8375 47 101111 1.2375 16 010000 0.8500 48 110000 1.2500 17 010001 0.8625 49 110001 1.2625 18 010010 0.8750 50 110010 1.2750 19 010011 0.8875 51 110011 1.2875 20 010100 0.9000 52 110100 1.3000 21 010101 0.9125 53 110101 1.
PAGE 47
Functional Block Description Table 36. SW1A/B Electrical Specification Characteristics noted under conditions BP = VSW1xIN = 3.6 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP = VSW1xIN = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max - - 500 • PLLX = 0 - 2.0 - • PLLX = 1 - 4.0 - • APS Mode, IL=0 mA; device not switching - 160 - • PFM Mode, IL=0 mA - 15 - • PFM, 0.9 V, 1.0 mA - 54 - • PWM, 1.
PAGE 48
Functional Block Description 7.5.4.4 SW2 SW2 is a fully integrated synchronous buck PWM voltage mode controlled DC/DC regulator. BP SW2IN SW2MODE ISENSE CINSW 3 SW2 Controller SW2LX Driver LSW2 C OSW2 D SW 2 SW2FAULT GNDSW2 Internal Compensation SW2FB SPI Interface SPI Z2 Z1 EA DAC V REF Figure 10. SW2 Block Diagram The peak current is sensed internally for over-current protection purposes.
PAGE 49
Functional Block Description Table 37. SW2 Output Voltage Programmability Set Point SW2[5:0] SW2x Output (V) Set Point SW2[5:0] SW2 Output (V) 17 010001 0.8625 49 110001 1.2625 18 010010 0.8750 50 110010 1.2750 19 010011 0.8875 51 110011 1.2875 20 010100 0.9000 52 110100 1.3000 21 010101 0.9125 53 110101 1.3125 22 010110 0.9250 54 110110 1.3250 23 010111 0.9375 55 110111 1.3375 24 011000 0.9500 56 111000 1.3500 25 011001 0.9625 57 111001 1.
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Functional Block Description Table 38. SW2 Electrical Specifications Characteristics noted under conditions BP = VSW2IN = 3.6 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP = VSW2IN = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit • APS Mode, IL=0 mA; device not switching - 160 - µA • PFM Mode, IL = 0 mA; device not switching - 15 - • PFM, 0.9 V, 1.0 mA - 54 - • PWM, 1.2 V, 120 mA - 75 - • PWM, 1.
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Functional Block Description Table 39. SW3 Output Voltage Programmability Set Point SW3[4:0] SW3 Output (V) Set Point SW3[4:0] SW3 Output (V) 0 00000 0.650 16 10000 1.050 1 00001 0.675 17 10001 1.075 2 00010 0.700 18 10010 1.100 3 00011 0.725 19 10011 1.125 4 00100 0.750 20 10100 1.150 5 00101 0.775 21 10101 1.175 6 00110 0.800 22 10110 1.200 7 00111 0.825 23 10111 1.225 8 01000 0.850 24 11000 1.250 9 01001 0.875 25 11001 1.275 10 01010 0.
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Functional Block Description Table 40. SW3 Electrical Specification Characteristics noted under conditions BP = VSW3IN = 3.6 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP = VSW3IN = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit • PLLX = 0 - 2.0 - MHz • PLLX = 1 - 4.0 - • APS Mode, IL=0 mA; device not switching - 160 - • PFM Mode, IL = 0 mA; device not switching - 15 - • PFM, 1.2 V, 1.
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Functional Block Description 7.5.4.6 SW4 SW4A/B is a fully integrated synchronous buck PWM voltage mode controlled DC/DC regulator. It can be operated in single/dual phase mode or as independent outputs. The operating mode of the switching regulator is configured by the SW4CFG pin. The SW4CFG pin is sampled at start-up. Table 41.
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Functional Block Description BP SW4IN SW4AMODE ISENSE CINSW4A SW4 SW4ALX LSW4A Controller Driver DSW4 COSW4a SW4AFAULT GNDSW4A Internal Compensation SW4AFB SPI Z2 Z1 VREF EA DAC SPI Interface BP SW4BIN SW4BMODE ISENSE CINSW4B SW4BLX Controller Driver SW4BFAULT GNDSW4B Internal Compensation SW4BFB SPI Z2 Z1 EA VCOREDIG VREF DAC SW4CFG Figure 13.
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Functional Block Description BP SW4AIN SW4AMODE ISENSE CINSW4A SW4 SW4ALX LSW4A Controller Driver DSW4A COSW4A SW4AFAULT GNDSW4A Internal Compensation SW4AFB SPI Z2 Z1 VREF EA DAC SPI Interface BP SW4BIN SW4BMODE ISENSE CINSW4B SW4BLX LSW4B Controller Driver DSW4B COSW4B SW4BFAULT GNDSW4B Internal Compensation SW4BFB SPI Z2 Z1 EA VCORE VREF DAC SW4CFG Figure 14. SW4 Dual Phase Output Mode Block Diagram The peak current is sensed internally for over-current protection purposes.
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Functional Block Description Table 43. SW4A/B Output Voltage Programmability Set Point SW4x[4:0] SW4x Output (V) 0 00000 1.200 16 10000 1.600 1 00001 1.225 17 10001 1.625 2 00010 1.250 18 10010 1.650 3 00011 1.275 19 10011 1.675 4 00100 1.300 20 10100 1.700 5 00101 1.325 21 10101 1.725 6 00110 1.350 22 10110 1.750 7 00111 1.375 23 10111 1.775 8 01000 1.400 24 11000 1.800 9 01001 1.425 25 11001 1.825 10 01010 1.450 26 11010 1.
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Functional Block Description Table 44. SW4A/B Electrical Specifications Characteristics noted under conditions BP=VSW4xIN = 3.6 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP=VSW4xIN = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit • PLLX = 0 - 2.0 - MHz • PLLX = 1 - 4.0 - • APS Mode, IL=0 mA; device not switching - 160 - • PFM Mode, IL = 0 mA; device not switching - 15 - • PFM, 3.
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Functional Block Description 7.5.4.7 SW5 SW5 is a fully integrated synchronous buck PWM voltage mode controlled DC/DC regulator. BP SW5IN SW5MODE ISENSE CINSW5 SW5 Controller SW5LX Driver LSW5 COSW5 DSW5 SW5FAULT GNDSW5 Internal Compensation SW5FB SPI Interface SPI Z2 Z1 VREF EA DAC Figure 15. SW5 Block Diagram The peak current is sensed internally for over-current protection purposes.
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Functional Block Description Table 46. SW5 Electrical Specifications Characteristics noted under conditions BP=VSW5IN = 3.6 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP=VSW5IN = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit • PWM operation, 0 mA < IL < IMAX 3.0 - 4.5 V • PFM operation, 0 mA < IL < ILMAX 2.8 - 4.
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Functional Block Description 7.5.4.8 Dynamic Voltage Scaling To reduce overall power consumption, processor core voltages can be varied depending on the mode or activity level of the processor. SW1A/B and SW2 allow for two different set points with controlled transitions to avoid sudden output voltage changes, which could cause logic disruptions on their loads. Preset operating points for SW1A/B and SW2 can be set up for: • Normal operation: output value selected by SPI bits SWx[5:0], refer to Table 47.
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Functional Block Description Request ed Set Point Output Voltage wit h light Load Internally Cont rolled Steps Example Actual Output Voltage Output Voltage Init ial Set Point Actual Output Voltage Internally Controlled St eps Request for Higher Voltage Voltage Change Request Possible Output Voltage Window Request for Lower Voltage I nit iated by SPI Programming, Standby Control SWxP WGD Figure 16. Voltage Stepping with DVS 7.5.
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Functional Block Description SWBST can be controlled by SPI programming in PFM, APS, and Auto mode. Auto mode transitions between PFM and APS mode based on the load current. By default SWBST is powered up in Auto mode. Table 50. SWBST Mode Control Parameter Voltage SWBST Mode 00 Off SWBSTMODE[1:0] 01 PFM SWBSTSTBYMODE[1:0] 10 Auto (default) 11 APS Table 51. SWBST Electrical Specifications Characteristics noted under conditions BP = SWBSTIN = 3.6 V, - 40 C  TA  85 C, unless otherwise noted.
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Functional Block Description Table 51. SWBST Electrical Specifications Characteristics noted under conditions BP = SWBSTIN = 3.6 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP = SWBSTIN = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max - 35 - - 1.0 6.0 Unit Notes SWITCH MODE SUPPLY SWBST (CONTINUED) ISWBSTBIAS ILEAK-SWBST Bias Current Consumption • PFM or Auto mode NMOS Off Leakage • SWBSTIN = 4.
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Functional Block Description The regulators can be disabled and the general purpose outputs can be forced low when going into Standby, note that the Standby response timing can be modified with the STBYDLY function, as described in the Power Saving section. Each regulator has an associated SPI bit for this. When the bit is not set, STANDBY is of no influence.
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Functional Block Description 7.5.6.3 Transient Response Waveforms The transient load and line response are specified with the waveforms depicted in Figure 18. Note, the transient load response refers to the overshoot only, and excludes the DC shift. The transient line response refers to the sum of both, overshoot and DC shift. These conditions are also valid for the mode transition response. VNOM + 0.8V IMAX VIN IL VNOM + 0.
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Functional Block Description 7.5.6.5 VPLL VPLL is provided for isolated biasing of the application processors’ PLLs that serves as the clock generation in support of protocol and peripheral needs. Depending on the application and power requirements, this supply may be considered for sharing with other loads, but noise injection must be avoided and filtering added if necessary to ensure suitable PLL performance. The VPLL regulator has a dedicated input supply pin.
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Functional Block Description Table 55. VPLL Electrical Specification Characteristics noted under conditions BP = 3.6 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max • Enable to 90% of end value VINPLL = VINMIN, VINMAX; IL = 0 mA - - 140 0.05 - 10 - 1.0 2.0 - 50 70 - 5.0 8.
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Functional Block Description Table 56. VREFDDR Electrical Specification Characteristics noted under conditions BP = 3.6 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol tOFFVREFDDR Characteristic Min Typ Max 0.05 - 10 - 1.0 2.0 - 5.
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Functional Block Description 7.5.6.8 VUSB2 VUSB2 has an internal PMOS pass FET to support light loads. An external PNP configuration is offered to avoid excess on-chip power dissipation at high loads and large differentials between BP and output settings. The input pin for the integrated PMOS option is shared with the base current drive pin for the external PNP option. The external PNP configuration must be committed as a hardwired board level implementation.
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Functional Block Description Table 59. VUSB2 Electrical Specification Characteristics noted under conditions BP = 3.6 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit VNOM - 3% VNOM VNOM + 3% 0.0 - 3.0 - 8.0 - • VUSB2IN = VINMIN + 100 mV - 30 - • VUSB2IN = VNOM + 1.0 V - 30 - - - 1.0 0.05 - 10 - 1.0 2.0 • VUSB2=01, 10, 11 - 1.0 2.
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Functional Block Description 20% in series with the output capacitance is required. The total resistance includes the ESR of the capacitor plus an external resistance provided by a discrete resistor or PCB circuit trace. The nominal output voltage of this regulator can be configured through SPI and can be 2.5 V, 2.6 V, 2.7 V, or 2.775 V. The maximum output current along the external PNP is 250 mA. Table 60. VDAC Voltage Control Parameter Value Output Voltage ILoad max 00 2.500 V 250 mA 01 2.
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Functional Block Description Table 61. VDAC Electrical Specification Characteristics noted under conditions BP = 3.6 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol tOFF-VDAC Characteristic Min Typ Max 0.05 - 10 - 1.0 2.0 - 1.0 2.0 - 5.0 8.0 - - 100 - 1.0 2.
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Functional Block Description Table 62. VGEN1 Control Register Bit Assignments VGEN1[2:0] 000 1.20 250 mA 001 1.25 250 mA 010 1.30 250 mA 011 1.35 250 mA 100 1.40 250 mA 101 1.45 250 mA 110 1.50 250 mA 111 1.55 250 mA Table 63. VGEN2 Control Register Bit Assignments Parameter VGEN2[2:0] Value Output Voltage 000 ILoad max VGEN2CONFIG=0 Internal Pass FET VGEN2CONFIG=1 External PNP 2.50 50 mA 250 mA 001 2.70 50 mA 250 mA 010 2.80 50 mA 250 mA 011 2.
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Functional Block Description Table 64. VGEN1 Electrical Specification Characteristics noted under conditions BP = 3.6 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit • IL = 75% of ILMAX 20 Hz to 20 kHz VGEN1[2:0] = 000-101 - 50 - dB • IL = 75% of ILMAX 20 Hz to 20 kHz VGEN1[2:0] = 110-111 - 45 - - - 1.0 0.01 - 10 - 1.0 2.0 - 1.0 2.0 - 5.0 8.
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Functional Block Description Table 65. VGEN2 Electrical Specification Characteristics noted under conditions BP = 3.6 V, - 40 C  TA  85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol VGEN2LOPP VGEN2LIPP IGEN2Q Characteristic Min Typ Max • 1.0 mA < IL < ILMAX - 0.20 - • Line Regulation - 8.0 - - 30 - 2.4 3.8 5.5 VNOM - 3% VNOM VNOM + 3% V 0.0 - 3.0 mA - 8.
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Functional Block Description 7.6 Analog to Digital Converter The ADC core is a 10 bit converter, supplied from VCORE. The ADC core and logic run at an internally generated frequency of approximately 1.33 MHz and has an integrated auto calibration circuit which reduces the offset and gain errors. 7.6.1 Input Selector The ADC has a total of 16 input channels (nine internal and seven external). Table 66 gives an overview of the characteristics of each of these channels. Table 66.
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Functional Block Description 7.6.2 Control The ADC parameters are programmed by the processor via the SPI. When a reading sequence is finished, an interrupt ADCDONEI is generated. The interrupt can be masked with the ADCDONEM bit. The ADC is enabled by setting ADEN bit high, then the ADC can start a series of conversions through SPI programming by setting the ADSTART bit. If the ADEN bit is low, the ADC will be disabled and in low-power mode.
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Functional Block Description 7.6.3 7.6.3.1 Dedicated Readings Channel 0 to 2 Reserved Channel 0 to Channel 2 are reserved. 7.6.3.2 Channel 3 Die Temperature The relation between the read out code and temperature is given in Table 69. Table 69. Die Temperature Voltage Reading Parameter Min Typ Max Unit Die temperature read out code at 25 °C - 680 - Decimal Slope temperature change per LSB - +0.426 - °C/LSB Slope error - - 5.
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Functional Block Description If the touchscreen is not used, the inputs TSX1, TSX2, TSY1, and TSY2 can be used as general purpose ADC inputs. They are respectively mapped on ADC channels 12, 13, 14, and 15. Touch Screen Pen detection bias can be enabled via the TSPENDETEN bit in the AD0 register. When this bit is enabled and a pen touch is detected, the TSPENDET bit in the Interrupt STATUS 0 register is set and the INT pin is asserted - unless the interrupt is masked.
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Functional Block Description Table 72. TSDLYx[3:0] TSDLYx[3:0] Delay in uS 0101 200 0110 240 0111 280 1000 320 1001 360 1010 400 1011 440 1100 480 1101 520 1110 560 1111 600 To perform a touch screen reading, the processor must do the following: 1. Enable the touch screen with TSEN 2. Select the touch screen sequence by programming the TSSEL0-TSSEL7 SPI bits. 3. Program the TSSTOP[2:0] 4. Program the delay between the conversion via the TSDLY1 and TSDLY2 settings. 5.
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Functional Block Description 7.7 7.7.1 Auxiliary Circuits General Purpose I/Os The 34709 contains four configurable GPIO input/outputs for general purpose use. When configured as outputs, they can be configured as open-drain (OD) or CMOS (push-pull outputs). These GPIOs are low-voltage capable (1.2 or 1.8 V). In open-drain configuration these outputs can only be pulled up to 2.5 V maximum. Each individual GPIO has a dedicated 16-bit control register. Table 74 provides the detailed bit descriptions.
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Functional Block Description Table 74. GPIOLVx Control (60) SPI Bit SRE[1:0] Description Slew rate enable 00: slow (default) 01: normal 10: fast 11: very fast Notes 60. x= 0, 1, 2, or 3 depending of the GPIO channel it is being used 7.7.2 PWM Outputs There are two PWM outputs on the 34709 PWM1 and PWM2 and which are controlled by the PWMxDUTY and PWMxCLKDIV registers shown in Table 75.The base clock will be the 2.0 MHz divided by 32. Table 75.
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Functional Block Description 7.8 Serial Interfaces The IC contains a number of programmable registers for control and communication. The majority of registers are accessed through a SPI interface in a typical application. The same register set may alternatively be accessed with an I2C interface that is muxed on SPI pins. Table 77 describes the muxed pin options for the SPI and I2C interfaces; further details for each interface mode follow. Table 77.
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Functional Block Description enough to clock all 24 data bits properly. To start a new SPI transfer, the CS line must be toggled low and then pulled high again. The MISO line will be tri-stated while CS is low. The register map includes bits that are read/write, read only, read/write “1” to clear (i.e., Interrupts), and clear on read, reserved, and unused. Refer to the SPI/I2C Register Map and the individual subcircuit descriptions to determine the read/write capability of each bit.
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Functional Block Description Table 78.
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Functional Block Description 7.8.2.3 I2C Operation The I2C mode of the interface is implemented generally following the Fast Mode definition which supports up to 400 kbits/s operation. (Exceptions to the standard are noted to be 7-bit only addressing, and no support for general Call addressing) Timing diagrams, electrical specifications, and further details on this bus standard, is available on the internet, by typing  “I2C specification” in the web search string field.
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Functional Block Description Packet Type Host SDA (to MISO) Device Address Register Address 23 START 16 15 0 0 Device Address 8 7 0 0 START R /W R /W Slave SDA (from MISO) A C K 16 Host can also drive another Start instead of Stop Device Data AP Lite Driven Data ( byte 0) A C K 23 A C K Device Data AP Lite Driven Data ( byte 1 ) Host SDA (to MISO) Slave SDA (from MISO) A C K Device Data AP Lite Driven Data ( byte 2) Packet Type Continuation 1 A C K 15 8 NA CK 7 STOP 0 Fig
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Functional Block Description 7.9 Configuration Registers 7.9.1 Register Set structure The general structure of the register set is given in Table 80. Expanded bit descriptions are included in the following functional sections for application guidance.
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Functional Block Description 7.9.2 7.9.2.1 Specific Registers IC and Version Identification The IC and other version details can be read via the identification bits. These are hardwired on the chip and described in Table 81. Table 81. IC Revision Bit Assignment Identifier 7.9.2.2 Value Purpose FULL_LAYER_REV[2:0] XXX Represents the full mask revision Pass 1.0 = 001 METAL_LAYER_REV[2:0] XXX Represents the full Metal revision Pass 1.1 = 001 Pass 1.
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Functional Block Description SPI/I2C Register Map 7.9.3 The complete SPI bitmap is given in Table 82. Table 82.
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Functional Block Description 0x05 0x06 Interrupt Sense 1 Table 88 Power Up Mode Sense Table 89 RO RO hXX_XX_XX h00_00_XX 23 22 21 20 19 18 17 16 - - - GPIOLV3S GPIOLV2S GPIOLV1S GPIOLV0S 8 15 14 13 12 11 10 9 CLKS THERM130S THERM125S THERM120S THERM110S - - - 7 6 5 4 3 2 1 0 - - - PWRON2S PWRON1S - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - PUMS5S PUMS
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Functional Block Description 23 22 21 20 19 18 17 16 10 9 8 3 2 1 0 19 18 17 16 10 9 8 3 2 1 0 19 18 17 16 10 9 8 3 2 1 0 19 18 17 16 10 9 8 3 2 1 0 19 18 17 16 11 10 9 8 3 2 1 0 MEMA[23:16] 0x10 Memory A Table 97 15 R/W 14 13 12 h00_00_00 11 MEMA[15:8] 7 6 5 4 23 22 21 20 MEMA[7:0] MEMB[23:16] 0x11 Memory B Table 98 R/W 15 14 13 12 7 6 5 4 h00_00_00 11 MEMB[15:8] MEMB[7:0] 23 22 21 20 15 14 13 12 MEMC[23:16]
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Functional Block Description 23 22 21 20 19 18 17 RSVD[5:0] 0x18 Regulator 1A/B Voltage R/WM hXX_XX_XX Table 105 15 14 13 12 11 6 5 4 3 22 21 20 19 15 14 7 6 R/WM hXX_XX_XX 0x1C R/WM 3 2 1 0 18 17 16 10 9 SW2STBY[5:2] 14 13 12 19 SW4BSTBY[4:0] SW4AHI[1:0] 6 5 4 3 2 19 18 17 - - - - - - - - 15 14 13 12 11 10 9 8 - - 6 5 4 3 2 1 0 20 19 18 17 16 - SW5TBY[4:0] - - - 23 22 21 PLLX PLLEN 15 14 h52_80_48 SW2UOMODE SW2
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Functional Block Description 0x20 0x21 0x22 Regulator Mode 0 Table 113 GPIOLV0 Control Table 114 GPIOLV1 Control R/WM h0X_XX_XX R/W R/W h00_38_0X h00_38_0X Table 115 0x23 GPIOLV2 Control R/W h00_38_0X Table 116 0x24 GPIOLV3 Control R/W h00_38_0X Table 117 0x25 to 0x2A 0x2B Unused ADC 0 Table 120 NU R/W h00_00_00 h00_00_00 23 22 21 20 19 18 17 16 - - - VUSB2MODE VUSB2STBY VUSB2EN VUSB2CONFIG VPLLSTBY 8 15 14 13 12 11 10 9 VPLLEN VGEN2MODE VGEN2STBY VGE
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Functional Block Description 23 22 21 20 19 18 ADSEL5[3:0] 0x2D ADC 2 Table 122 15 R/W 14 h00_00_00 13 12 11 10 ADSEL3[3:0] 7 6 23 22 5 4 3 2 21 20 19 18 15 R/W h00_00_00 TSSEL6[1:0] 14 13 6 5 TSSEL3[1:0] 8 1 0 17 TSSEL5[1:0] 12 11 4 3 TSSEL2[1:0] 7 9 ADSEL0[3:0] TSSEL7[1:0] ADC 3 Table 123 16 ADSEL2[3:0] ADSEL1[3:0] 0x2E 17 ADSEL4[3:0] 16 TSSEL4[1:0] 10 9 2 1 0 18 17 16 10 9 8 TSSEL1[1:0] 8 TSSEL0[1:0] ADSEL7[3:0] ADSEL6[3:0] 23 22 21
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Functional Block Description 0x35 to 0x36 Unused NU 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 h00_00_00 - - - - - - - - 23 22 21 20 19 18 17 16 15 14 12 11 10 9 4 3 2 PWM2CLKDIV[5:0] PWM Control Table 131 0x37 R/W h00_00_00 13 PWM2DUTY[5:4] PWM2DUTY[3:0] 7 6 PWM1CLKDIV[5:2] 5 PWM1CLKDIV[1:0] 23 0x38 to 0x3F Unused 7.9.
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Functional Block Description Table 85. Register 2, Reserved Name Bit # R/W Reset Default Reserved 23-0 R - - Description Reserved Back to SPI/I2C Register Map Table 86. Register 3, Interrupt Status 1 Name Bit # R/W Reset Default Description 1HZI 0 RW1C RTCPORB 0 1.
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Functional Block Description Table 87.
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Functional Block Description Table 89. Register 6, Power-up Mode Sense Name Bit # R/W Reset Default ICTESTS 0 R NONE S ICTEST sense state PUMS1S 1 R NONE L PUMS1 state PUMS2S 2 R NONE L PUMS2 state PUMS3S 3 R NONE L PUMS3 state PUMS4S 4 R NONE L PUMS4 state PUMS5S 5 R NONE L PUMS5 state Unused 8-6 R 0 Not available Reserved 9 R - Reserved Unused 23-10 R 0 Not available - Description Back to SPI/I2C Register Map Table 90.
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Functional Block Description Table 91.
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Functional Block Description Table 94.
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Functional Block Description Table 96.
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Functional Block Description Table 97.
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Functional Block Description Table 98.
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Functional Block Description Table 99.
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Functional Block Description Table 100.
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Functional Block Description Table 101.
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Functional Block Description Table 102.
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Functional Block Description Table 103.
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Functional Block Description Table 104.
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Functional Block Description Table 106.
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Functional Block Description Table 107.
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Functional Block Description Table 109.
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Functional Block Description Table 110.
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Functional Block Description Table 112. Register 31, SWBST Control Name Bit # R/W Reset Default Description SWBST0 0 R/W NONE * SWBST1 1 R/W NONE * SWBSTMODE0 2 R/W RESETB 0 SWBSTMODE1 3 R/W RESETB 1 Spare 4 R/W RESETB 0 SWBSTSTBYMODE0 5 R/W RESETB 0 SWBSTSTBYMODE1 6 R/W RESETB 1 Spare 7 R/W RESETB 0 Not available Unused 8 - 23 R 0 Not available SWBST setting SWBST mode Not available SWBST standby mode Back to SPI/I2C Register Map Table 113.
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Functional Block Description Table 114.
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Functional Block Description Table 115.
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Functional Block Description Table 116.
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Functional Block Description Table 117.
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Functional Block Description Table 118. Register 37 - 40, Reserved Name Bit # R/W Unused 0 - 23 R Reset Default 0 Description Not available Table 119. Register 41 - 42, Unused Name Bit # R/W Unused 0-23 R Reset Default 0 Description Not available Table 120.
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Functional Block Description Table 121.
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Functional Block Description Table 122.
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Functional Block Description Table 123. Register 46, ADC 3 Name Bit # R/W Reset Default TSSEL40 16 R/W DIGRESETB 0 TSSEL41 17 R/W DIGRESETB 0 TSSEL50 18 R/W DIGRESETB 0 TSSEL51 19 R/W DIGRESETB 0 TSSEL60 20 R/W DIGRESETB 0 TSSEL61 21 R/W DIGRESETB 0 TSSEL70 22 R/W DIGRESETB 0 TSSEL71 23 R/W DIGRESETB 0 Reset Default Description Touch screen Selection to place in ADRESULT4. See TSSEL0 for modes. Touch screen Selection to place in ADRESULT5.
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Functional Block Description Table 125.
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Functional Block Description Table 126.
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Functional Block Description Table 127.
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Functional Block Description Table 130. Register 53 - 54, Reserved Name Bit # R/W Unused 0 - 23 R Reset Default 0 Description Not Available Table 131.
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Typical Applications 8 Typical Applications Figure 24 gives a typical application diagram of the 34709 PMIC together with its functional components. For details on component references and additional components such as filters, refer to the individual sections. 8.1 Application Diagram O/P Drive SW1 Dual Phase GP 2000 mA Buck GNDADC 10 Bit GP ADC ADIN9 General Purpose ADC Inputs: i.e., PA thermistor, Light Sensor, Etc.
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Typical Applications 8.2 Bill of Material Table 133 provides a complete list of the recommended components on a full featured system using the 34709 Device. Critical components such as inductors, transistors, and diodes are provided with a recommended part number, but equivalent components may be used. Table 133.
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Typical Applications Table 133. 34709 Bill of Material (74) Item Reference Quantity Description Vendor Comments 22 L2 1 23 C6 1 22 F Buck 2 Output Capacitor 24 C5 1 4.7 F Buck 2 Input Capacitor 25 D2 1 26 L3 1 27 C8 1 10 F Buck 3 Output Capacitor 28 C7 1 4.7 F Buck 3 Input Capacitor 29 D3 1 L4A 1 SW2 1.0 H • VLS252010ET-1R0N Diode • BAS3010-03LRH TDK Buck 2 Inductor Infineon SW2LX diode TDK Buck 3 Inductor SW3 1.
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Typical Applications Table 133. 34709 Bill of Material (74) Item Reference Quantity Description Vendor Comments C20 1 2.2 F VPLL output capacitor 43 C18 1 100 nF VHALF 0.1 F capacitor 44 C19 1 1.0 F VREFDDR output Capacitor 45 C17 1 100 nF VINREFDDR/VHALF decoupling capacitor 46 C35 1 1.0 F VREFDDR input Capacitor 47 Q2 1 PNP NSS12100UW3TCG PNP NSS12100XV6T1G 2SB1733 48 C22 1 2.
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Typical Applications 8.3 34709 Layout Guidelines 8.3.1 1. • • • • General board recommendations It is recommended to use an 4 layer board stack-up arranged as follows: High-current signal GND Signal High-current signal 2. Allocate TOP and BOTTOM PCB Layers for POWER ROUTING (high-current signals), copper-pour the unused area. 3. Add one GND inner layer to reduce Current loops to the maximum between layers. 8.3.2 1.
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Typical Applications 2. The crystal connected to the XTAL1 and XTAL2 pins must not have a ground plane directly below. 3. The following are clock signals: CLK, CLK32K, CLK32KMCU, XTAL1, and XTAL2. These signals must not run parallel to each other, or in the same routing layer.
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Typical Applications Figure 27. Recommended Layout for Switching Regulators.
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Packaging 9 Packaging 9.1 Packaging Mechanical Dimensions Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.freescale.com and perform a keyword search for the drawing’s document number. Table 134. Package Drawing Information Package Suffix 130-pin MAPBGA (8 x 8 mm), 0.
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Packaging VK SUFFIX 130-PIN 98ASA00333D REVISION 0 Figure 28.
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Packaging VK SUFFIX 130-PIN 98ASA00333D REVISION 0 Figure 29.
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Reference Section 10 Reference Section Table 135.
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Revision History 11 Revision History REVISION DATE 1.0 8/2012 2.0 10/2012 DESCRIPTION OF CHANGES • Initial release • Corrected doc number to MC34709, corrected part number PC34709VK • Deleted columns Rating and Balls from Table 3 • Updated table 4 with Maximum Rating for all pins • Updated BP max rating to 4.8 • Updated LICELL Max rating to 3.8V • Added table 7.
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How to Reach Us: Information in this document is provided solely to enable system and software Home Page: freescale.com implementers to use Freescale products. There are no express or implied copyright Web Support: freescale.com/support information in this document. licenses granted hereunder to design or fabricate any integrated circuits on the Freescale reserves the right to make changes without further notice to any products herein.