Datasheet

Analog Integrated Circuit Device Data
Freescale Semiconductor 128
34709
Typical Applications
8 Typical Applications
Figure 24 gives a typical application diagram of the 34709 PMIC together with its functional components. For details on
component references and additional components such as filters, refer to the individual sections.
8.1 Application Diagram
Figure 24. Typical Application Schematic
BP
RESETB
RESETBMCU
WDI
Switchers
GNDADC
ADIN11
MUX
10 Bit GP
ADC
INT
CLK32K
XTAL1 XTAL2
GNDRTC
LICELL
GPIO Control
GPIOLV1 GPIOLV2
RTC +
Calibration
GNDSW2
SW2FB
SW2LX
SW1IN
SW2IN
O/P
Drive
`
GNDSW1A
SW1FB
SW3IN
O/P
Drive
GNDSW3
SW3FB
SW3LX
GNDSWBST
SWBSTFB
SWBSTIN
SWBSTLX
O/P
Drive
PWRON1
PUMS1
Monitor
Timer
O/P
Drive
PLL
32 KHz
Crystal
Osc
STANDBY
GPIOLV3
LCELL
Switch
Enables &
Control
SPI Result
Registers
Interrupt
Inputs
GNDCTRL
Core Control Logic , Timers, & Interrupts
32 KHz
Internal
Osc
GPIOLV4
ADIN10
CLK32KMCU
GNDREG1
GNDREG2
ADIN9
A/D Result
A/D
Control
ICTEST
32 KHz
Buffers
Output Pin
Input Pin
Bi-directional Pin
Package Pin Legend
SPI
Interface
+
Muxed
I2C
Optional
Interface
CS
CLK
GNDSPI
MISO
SPI
Registers
MOSI
Shift Register
Shift Register
SPIVCC
To Enables & Control
To
Trimmed
Circuits
SPI
Control
Logic
Trim-In-Package
Startup
Sequencer
Decode
Trim?
PUMSx
Control
Logic
Li Cell
Charger
SW2
LP
1000 mA
Buck
SW3
INT MEM
500 mA
Buck
SWBST
380 mA
Boost
34709
SW4
Dual Phase
DDR
1000 mA
Buck
VSRTC
VSRTC
VINREFDDR
VPLL
VPLL
50 mA
Pass
FET
VREFDDR
10mA
VREFDDR
VINUSB
VUSB
Best
of
Supply
LICELL
BP
Reference
Generation
VCOREDIG
GNDCORE
VCORE
VCOREREF
VUSB
Regulator
SUBSANA1
SUBSPWR1
SUBSREF
SUBSGND
SUBSPWR2
SUBSANA3
SUBSANA2 SUBSLDO
VINPLL
PUMS2
PWRON2
GLBRST
SW5IN
O/P
Drive
GNDSW5
SW5FB
SW5LX
SW5
I/O
1000 mA
Buck
VUSB2
350mA
VDACDRV
VDAC
VUSB2
VUSB2DRV
VDAC
250mA
SW1ALX
DVS
CONTROL
SW1PWGD
SW2PWGD
PWM
Outputs
PWM1 PWM2
GNDSW1B
O/P
Drive
SW1BLX
SW4AIN
GNDSW4A
SW4FBA
O/P
Drive
SW4ALX
SW4BIN
GNDSW4B
SW4BFB
O/P
Drive
SW4BLX
GNDUSB
SW4CFG
VDDLP
VGEN1
250mA
VGEN2DRV
VGEN2
VGEN2
250mA
Pass
FET
VGEN1
Pass
FET
VINGEN1
PUMS3
PUMS4
SDWNB
Digital Core
BP
SW1
Dual Phase
GP
2000 mA
Buck
SW1CFG
SW1VSSSNS
VHALF
PUMS5
GPIOVDD
GNDGPIO
GNDREF1
GNDREF2
GNDREF
LDOVDD
Pass
FET
100n
Coin Cell
Battery
2.2u
SWBST
100pF
1u
1u
SPI
SW5
General Purpose
ADC Inputs:
i.e., PA thermistor,
Light Sensor, Etc.
100n
10u
BP
2x22u
SWBST
Output
(Boost)
2.2u
4.7u
BP
SW4B
1u
BP
2.2u
1.0u
2 x22u
SW1 Output
BP
4.7u
BP
4.7u
1.0u
22u
SW2 Output
To AP
BP
4.7u
1.0u
10u
SW3 Output
1.0u
22u
SW4A Output
BP
4.7u
4.7u
1.0u
22u
SW4B Output
1.0u
22u
SW5 Output
BP
4.7u
To AP
2.2u
BP
2.2u
BP
SW5
2.2u
BP
4.7u
VCOREDIG
BP
100n
BP
To AP
To Peripherals
To GND, or
VCOREDIG
To/From
AP
On/Off
Button
Wakeup from AP
Reset
button
32.768 KHz
Crystal
18p
SW5 or SW3
0.1u
100K
100K
100K
100K
100K
ADIN14/TSY1
ADIN15/TSY2
ADIN13/TSX2
TSREF
Touch
Screen
Interface
ADIN12/TSX1
Touch
Screen
Interface
2.2u
100n
C1
C34
C33
C32
C31
C30
C29
C28
C2 L1A
C3/C4
R18
C5
L2
C6
R19
C7
L3
C8
C9
L4A
C10
C13
C12
L4B
C14
L5
L6
C15
D7
C16
C17
C18
C19
C20
C21
Q1
Q2
C22
C23
Q3
C24
C25
C27
R20R4
C26
18p
Y1
R3
C11
D1
D2
D3
D4
D5
D6
Main input Supply - BP
1u
C35
VIN
CE
VOUT
GND
VDDLP
100nF
100nF
C58
C59
D7
1.5V LDO
BP
D8
D9
LICELL
Workaround f or erratum #7
If back-up coin cell is not present in the applciation , D8 and D9
are not required and BP is connected directly to VIN of the LDO
R21
40m
R22
100m
R23
50m