Datasheet

Peripheral Register Memory Map and Reset Value
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor 101
40 0000 SIM SIM_CTRL 0 0 0 0 0 0 0 0 0 0
ONCEEBL
SW RST
STOP_
DISABLE
WAIT_
DISABLE
41 0001 SIM
SIM_
RSTAT
0 0 0 0 0 0 0 0 0SWR
COP_CPU
COP_LOR
EXTR
LVD R PP D P O R
42 01F2 SIM
SIM_
MSHID
SIM_MSH_ID
43 601D SIM
SIM_
LSHID
SIM_LSH_ID
45 2020 SIM
SIM_
CLKOUT
0 0
CLKDIS1
0 0 CLKOSEL1 0 0
CLKDIS0
CLKOSEL0
46 0000 SIM SIM_PCR
TMR_CR
0
PWM_CR
SCI_CR
0 0 0 0 0 0 0 0 0 0 0 0
47 0000 SIM SIM_PCE
CMP2 CMP1 CMP0
ADC1 ADC0 PGA1 PGA0
I2C SCI SPI PWM COP PDB PIT TA1 TA0
48 0000 SIM SIM_SDR
CMP2 CMP1 CMP0
ADC1 ADC0
PGA1 PGA0
I2C SCI SPI PWM COP PDB PIT TA1 TA0
49 F000 SIM SIM_ISAL ADDR_15_6 0 0 0 0 0 0
4A 0000 SIM SIM_PROT 0 0 0 0 0 0 0 0 0 0 0 0 PCEP GIPSP
4B 0000 SIM SIM_GPSA 0 0 0 0 0 0 0 GPS_A6 GPS_A5 GPS_A4 GPS_A3
4C 0000 SIM
SIM_
GPSB0
GPS_B5 GPS_B4 GPS_B3 GPS_B2
0 GPS_B1 GPS_B0
4D 0000 SIM
SIM_
GPSB1
0 0 0 0 0 0 0 0 0 0 0 0 GPS_B7 GPS_B6
Table 44. Detailed Peripheral Memory Map (continued)
Offset
Addr.
(Hex)
Reset
Value
(Hex)
Periph. Register
Bit
15
1413121110987654321
Bit
0