Datasheet

MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor102
Peripheral Register Memory Map and Reset Value
4E 0000 SIM SIM_GPSC 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPS_C6 GPS_C0
4F 0000 SIM SIM_GPSD 0 0 0 0 0 0 0 GPS_D3 GPS_D2 GPS_D1 GPS_D0
50 0000 SIM SIM_IPS0
0 0 0 0
IPS_FAULT3 IPS_FAULT2 IPS_FAULT1
IPS_PSRC2 IPS_PSRC1 IPS_PSRC0
51 0000 SIM SIM_IPS1
0 IPS_C2_WS IPS_C1_WS IPS_C0_WS IPS_T1 IPS_T0
52–5F — SIM Reserved RESERVED
60 0208 PMC PMC_SCR
OORF
LVD F
PPDF
PORF
OORIE
LVDI E
LVDRE
PPDE
LPR LPRS
LPWUI
BGBE
LVDE LV L S PROT
61 00--
2
PMC PMC_CR2 0 0 0 0 0 0 0
LPO_EN
LPO_TRIM TRIM
7F — PMC Reserved
RESERVED
80 0000 CMP0
CMP0_
CR0
0 0 0 0 0 0 0 0 0 FILTER_CNT PMC MMC
81 0000 CMP0
CMP0_
CR1
0 0 0 0 0 0 0 0SEWE0
PMODE
INV COS OPE EN
82 0000 CMP0
CMP0_
FPR
0 0 0 0 0 0 0 0 FILT_PER
83 0000 CMP0
CMP0_
SCR
0 0 0 0 0 0 0 0 0 0 0IERIEFCFRCFF
COUT
84–9F — CMP0 Reserved RESERVED
A0 0000 CMP1
CMP1_
CR0
0 0 0 0 0 0 0 0 0 FILTER_CNT PMC MMC
Table 44. Detailed Peripheral Memory Map (continued)
Offset
Addr.
(Hex)
Reset
Value
(Hex)
Periph. Register
Bit
15
1413121110987654321
Bit
0