Datasheet

Signal/Connection Descriptions
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor 17
Figure 7. Top View, MC56F8006 48-Pin LQFP Package
4.3 56F8006/56F8002 Signal Pins
After reset, each pin is configured for its primary function (listed first). Any alternate functionality must be programmed via the
GPIO module’s peripheral enable registers (GPIO_x_PER) and SIM module’s (GPS_xn) GPIO peripheral select registers. If
CLKIN or XTAL is selected as device external clock input, the CLK_MOD bit in the OCCS oscillator control register (OSCTL)
needs to be set too. EXT_SEL bit in OSCTL selects CLKIN or XTAL.
Orientation Mark
GPIOB6/RXD/SDA/ANA13 & CMP0_P2/CLKIN
GPIOB1/SS
/SDA/ANA12 & CMP2_P3
GPIOB7/TXD/SCL/ANA11 & CMP2_M3
GPIOB5/T1/FAULT3/SCLK
ANB8 and PGA1+ & CMP0_M2/GPIOC4
ANB6 and PGA1– & CMP0_P4/GPIOC5
ANB4 & CMP1_P1/GPIOC6/PWM2
V
DDA
V
SSA
ANA9 and PGA0– & CMP2_P4/GPIOC2
ANA7 & PGA0+ & CMP2_M2/GPIOC1
ANA5 & CMP1_M1/GPIOC0/FAULT0
V
SS
TCK/GPIOD2/ANA4 & CMP1_P2/CMP2_OUT
RESET
/GPIOA7
GPIOB3/MOSI/TIN3/ANA3 & ANB3/PWM5/CMP1_OUT
GPIOA3/PWM3/TXD/EXTAL
GPIOA2/PWM2
GPIOB0/SCLK/SCL/ANB13/PWM3/T1
GPIOA5/PWM5/FAULT2 or EXT_SYNC/TIN3
GPIOB4/T0/CLKO_0/MISO/SDA/RXD/ANA0 & ANB0
GPIOA6/FAULT0/ANA1 & ANB1/SCL/TXD/CLKO_1
GPIOB2/MISO/TIN2/ANA2 & ANB2/CMP0_OUT
TDO/GPIOD1/ANB10/T0/CMP2_OUT TMS/GPIOD3/ANB11/T1/CMP1_OUT TDI/GPIOD0/ANB12/SS
/TIN2/CMP0_OUT
GPIOA0/PWM0
GPIOA1/PWM1 V
SS
V
DD
GPIOF0/XTAL
GPIOA4/PWM4/SDA/FAULT1/TIN2
GPIOE0
GPIOE1/ANB9 & CMP0_P1
GPIOE2/ANB7 & CMP0_M1
GPIOC7/ANB5 & CMP1_M2
GPIOE3/ANA10 & CMP2_M1
GPIOE5/ANA8 & CMP2_P1
GPIOE4/ANA6 & CMP2_P2
V
DD
Vss
GPIOE6
V
DD
GPIOE7/CMP1_M3
GPIOF3/CMP0_P3
GPIOF2/CMP0_M3
GPIOF1/CMP1_P3
GPIOC3/EXT_TRIGGER
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24