Datasheet

MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Memory Maps
Freescale Semiconductor30
5.3 Data Map
The 56F8006/56F8002 series contain a dual access memory. It can be accessed from core primary data buses (XAB1; CDBW;
CDBR) and secondary data buses (XAB2; XDB2). Addresses in data memory are selected on the XAB1 and XAB2 buses. Byte,
word, and long data transfers occur on the 32-bit CDBR and CDBW buses. A second 16-bit read operation can be performed
in parallel on the XDB2 bus.
Peripheral registers and on-chip JTAG/EOnCE controller registers are memory-mapped into data memory access. A special
direct address mode is supported for accessing a first 64-location in data memory by using a single word instruction.
The data memory map is shown in Table 9.
Table 8. Program Memory Map
1
for 56F8002 at Reset (continued)
1
All addresses are 16-bit word addresses.
Begin/End Address Memory Allocation
P: 0x1F FFFF
P: 0x00 8800
RESERVED
P: 0x00 83FF
P: 0x00 8000
On-Chip RAM
2
: 2 KB
2
This RAM is shared with data space starting at address X: 0x00 0000; see Figure 9.
P: 0x00 7FFF
P: 0x00 2000
RESERVED
P: 0x00 1FFF
P: 0x00 0800
• Internal program flash: 12 KB
• Interrupt vector table locates from 0x00 0800 to 0x00 0865
• COP reset address = 0x00 0802
• Boot location = 0x00 0800
P: 0x00 07FF
P: 0x00 0000
RESERVED
Table 9. Data Memory Map
1
1
All addresses are 16-bit word addresses.
Begin/End Address Memory Allocation
X:0xFF FFFF
X:0xFF FF00
EOnCE
256 locations allocated
X:0xFF FEFF
X:0x01 0000
RESERVED
X:0x00 FFFF
X:0x00 F000
On-Chip Peripherals
4096 locations allocated
X:0x00 EFFF
X:0x00 8800
RESERVED
X:0x00 87FF
X:0x00 8000
RESERVED
X:0x00 7FFF
X:0x00 0400
RESERVED
X:0x00 03FF
X:0x00 0000
On-Chip Data RAM
2 KB
2
2
This RAM is shared with Program space starting at P: 0x00 8000. See Figure 8 and
Figure 9.