Datasheet

Specifications
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor 59
Figure 27. SPI Master Timing (CPHA = 0)
Data valid for outputs
Master
Slave (after enable edge)
t
DV
—
—
4.5
20.4
ns
ns
Figure 27,
Figure 28,
Figure 29,
Figure 30
Data invalid
Master
Slave
t
DI
0
0
—
—
ns
ns
Figure 27,
Figure 28,
Figure 29,
Figure 30
Rise time
Master
Slave
t
R
—
—
11.5
10.0
ns
ns
Figure 27,
Figure 28,
Figure 29,
Figure 30
Fall time
Master
Slave
t
F
—
—
9.7
9.0
ns
ns
Figure 27,
Figure 28,
Figure 29,
Figure 30
1
Parameters listed are guaranteed by design.
Table 29. SPI Timing
1
(continued)
Characteristic Symbol Min Max Unit See Figure
SCLK (CPOL = 0)
(Output)
SCLK (CPOL = 1)
(Output)
MISO
(Input)
MOSI
(Output)
MSB in Bits 14–1 LSB in
t
F
t
C
t
CL
t
CL
t
R
t
R
t
F
t
DS
t
DH
t
CH
t
DI
t
DV
t
DI
(ref)
t
R
Master MSB out Bits 14–1 Master LSB out
SS
(Input)
t
CH
SS is held high on master
t
F