Datasheet

Specifications
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor 61
Figure 30. SPI Slave Timing (CPHA = 1)
8.13.2 Serial Communication Interface (SCI) Timing
Table 30. SCI Timing
1
1
Parameters listed are guaranteed by design.
Characteristic Symbol Min Max Unit See Figure
Baud rate
2
2
f
MAX
is the frequency of operation of the SCI in MHz, which can be selected system clock (max. 32 MHz) or 3x system clock
(max. 96 MHz) for the 56F8006/56F8002 device.
BR — (f
MAX
/16) Mbps —
RXD pulse width RXD
PW
0.965/BR 1.04/BR ns Figure 31
TXD pulse width TXD
PW
0.965/BR 1.04/BR ns Figure 32
LIN Slave Mode
Deviation of slave node clock from
nominal clock rate before
synchronization
F
TOL_UNSYNCH
–14 14 % —
Deviation of slave node clock relative to
the master node clock after
synchronization
F
TOL_SYNCH
–2 2 % —
Minimum break character length T
BREAK
13 — Master node
bit periods
—
11 — Slave node
bit periods
—
SCLK (CPOL = 0)
(Input)
SCLK (CPOL = 1)
(Input)
MISO
(Output)
MOSI
(Input)
Slave MSB out Bits 14–1
t
C
t
CL
t
CL
t
CH
t
DI
MSB in Bits 14–1 LSB in
SS
(Input)
t
CH
t
DH
t
F
t
R
Slave LSB out
t
D
t
A
t
ELD
t
DV
t
F
t
R
t
ELG
t
DV
t
DS