Datasheet
Revision History
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor 83
11 Revision History
Table 41 lists major changes between versions of the MC56F8006 document.
Appendix A
Interrupt Vector Table
Table 43 provides the 56F8006/56F8002’s reset and interrupt priority structure, including on-chip peripherals. The table is
organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. As indicated, the priority of an
interrupt can be assigned to different levels, allowing some control over interrupt priorities. All level 3 interrupts are serviced
before level 2 and so on. For a selected priority level, the lowest vector number has the highest priority.
The location of the vector table is determined by the vector base address (VBA). Please see the MC56F8006 Peripheral
Reference Manual for detail.
By default, the chip reset address and COP reset address correspond to vector 0 and 1 of the interrupt vector table. In these
instances, the first two locations in the vector table must contain branch or JMP instructions. All other entries must contain JSR
instructions.
Table 41. Changes Between Revisions 2 and 3
Location Description
Introduction on page 1 Added part marking for devices covered by this document
Section 6.7, “PWM, PDB, PGA, and ADC
Connections,” on page 38
Updated routing details for ANB24 and ANB25
Tabl e 12 on page 42 Removed row about open drain mode (GPIO supports only push-pull mode)
Tabl e 21 on page 47 Updated specifications for low-voltage detection threshold (high and low range) and
low-voltage warning threshold
Tabl e 22 on page 51 Updated all Supply Current Consumption specifications
Tabl e 26 and Figure 22 on page 55 Updated ROSC variation over temperature specifications (both ranges)
Tabl e 31 on page 62 Removed I
2
C fast mode specifications and footnote about setup time if the TX FIFO
is empty (fast mode and FIFO not supported)
Appendix B on page 86 Added note explaining ADC and GPIO naming conventions
Tabl e 44 on page 86 For I2C_SMB_CSR, clarified that bits 7 and 6 are reserved
Table 42. Changes Between Revisions 3 and 4
Location Description
Throughout document. Added information for 32-pin PSDIP device and devices with temperature range
from –40 C to + 125 C.