Datasheet

MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor88
Peripheral Register Memory Map and Reset Value
1A 0000 TMR1
TMR1_
CSCTRL
DBG_EN
FAULT
ALT_LOAD
0 0 0 0
TCF2EN TCF1EN
TCF2 TCF1 CL2 CL1
1B 0000 TMR1
TMR1_
FILT
0 0 0 0 0 FILT_CNT FILT_PER
1C–1F — TMR1 Reserved
RESERVED
20 0000 PWM
PWM_
CTRL
LDFQ HALF
IPOL2 IPOL1 IPOL0
PRSC
PWMRIE
PWMF
ISENS
LDOK
PWMEN
21 0000 PWM
PWM_
FCTRL
0 0 0 0
FPOL3 FPOL2 FPOL1 FPOL0
FIE3
FMODE3
FIE2
FMODE2
FIE1
FMODE1
FIE0
FMODE0
22 0000 PWM
PWM_
FLTACK
FPIN3
FFLAG3
FPIN2
FFLAG2
FPIN1
FFLAG1
FPIN0
FFLAG0
FTACK3 FTACK2 FTACK1 FTACK0
23 0000 PWM
PWM_
OUT
PAD _E N
0
OUTCTL5 OUTCTL4 OUTCTL3 OUTCTL2 OUTCTL1 OUTCTL0
0 0
OUT5 OUT4 OUT3 OUT2 OUT1 OUT0
24 0000 PWM
PWM_
CNTR
0CR
25 0000 PWM
PWM_
CMOD
0PWMCM
26 0000 PWM
PWM_
VAL0
PMVAL
27 0000 PWM
PWM_
VAL1
PMVAL
28 0000 PWM
PWM_
VAL2
PMVAL
Table 44. Detailed Peripheral Memory Map (continued)
Offset
Addr.
(Hex)
Reset
Value
(Hex)
Periph. Register
Bit
15
1413121110987654321
Bit
0