Datasheet

MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor92
Peripheral Register Memory Map and Reset Value
8B 0000 ADC1
ADC1_
ADCRA
0
ADR11 ADR10
ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
0 0 0
8C 0000 ADC1
ADC1_
ADCRB
0
ADR11 ADR10
ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
0 0 0
8D–8F — ADC1 Reserved
RESERVED
A0 0000 PGA0
PGA0_
CNTL0
0 0 0 0 0 0 0 0 TM GAINSEL LP EN
A1 0002 PGA0
PGA0_
CNTL1
0 0 0 0 0 0 0 0
PPDIS
PA R MO DE
0CALMODE CPD
A2 000E PGA0
PGA0_
CNTL2
0 0 0 0 0 0 0 0 0 0
SWTRIG
NUM_CLK_GS ADIV
A3 0000 PGA0 PGA0_STS 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RUNNING
STCOMP
A4–BF — PGA0 Reserved RESERVED
C0 0000 PGA1
PGA1_
CNTL0
0 0 0 0 0 0 0 0 TM GAINSEL LP EN
C1 0002 PGA1
PGA1_
CNTL1
0 0 0 0 0 0 0 0
PPDIS
PA R MO DE
0CALMODE CPD
C2 000E PGA1
PGA1_
CNTL2
0 0 0 0 0 0 0 0 0 0
SWTRIG
NUM_CLK_GS ADIV
Table 44. Detailed Peripheral Memory Map (continued)
Offset
Addr.
(Hex)
Reset
Value
(Hex)
Periph. Register
Bit
15
1413121110987654321
Bit
0