Datasheet

MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor98
Peripheral Register Memory Map and Reset Value
C9 — GPIOC Reserved RESERVED
CA 0000 GPIOC
GPIOC_
RAWDATA
0 0 0 0 0 0 0 0RAWDATA
CB 0000 GPIOC
GPIOC_
DRIVE
0 0 0 0 0 0 0 0DRIVE
CC 00FF GPIOC
GPIOC_
IFE
0 0 0 0 0 0 0 0IFE
CD 0000 GPIOC
GPIOC_
SLEW
0 0 0 0 0 0 0 0SLEW
CE–DF — GPIOC Reserved
RESERVED
E0 00FF GPIOD
GPIOD_
PUR
0 0 0 0 0 0 0 0 0 0 0 0PUR
E1 0000 GPIOD GPIOD_DR
0 0 0 0 0 0 0 0 0 0 0 0DR
E2 0000 GPIOD
GPIOD_
DDR
0 0 0 0 0 0 0 0 0 0 0 0 DDR
E3 0080 GPIOD
GPIOD_
PER
0 0 0 0 0 0 0 0 0 0 0 0 PER
E4 — GPIOD Reserved
RESERVED
E5 0000 GPIOD
GPIOD_
IENR
0 0 0 0 0 0 0 0 0 0 0 0IENR
E6 0000 GPIOD
GPIOD_
IPOLR
0 0 0 0 0 0 0 0 0 0 0 0IPOLR
E7 0000 GPIOD
GPIOD_
IPR
0 0 0 0 0 0 0 0 0 0 0 0IPR
E8 0000 GPIOD
GPIOD_
IESR
0 0 0 0 0 0 0 0 0 0 0 0 IESR
E9 — GPIOD Reserved
RESERVED
EA 0000 GPIOD
GPIOD_
RAWDATA
0 0 0 0 0 0 0 0 0 0 0 0RAWDATA
Table 44. Detailed Peripheral Memory Map (continued)
Offset
Addr.
(Hex)
Reset
Value
(Hex)
Periph. Register
Bit
15
1413121110987654321
Bit
0