Datasheet

Peripheral Register Memory Map and Reset Value
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor 103
A1 0000 CMP1
CMP1_
CR1
0 0 0 0 0 0 0 0SEWE0
PMODE
INV COS OPE EN
A2 0000 CMP1
CMP1_
FPR
0 0 0 0 0 0 0 0 FILT_PER
A3 0000 CMP1
CMP1_
SCR
0 0 0 0 0 0 0 0 0 0 0IERIEFCFRCFF
COUT
A4–BF — CMP1 Reserved RESERVED
C0 0000 CMP2
CMP2_
CR0
0 0 0 0 0 0 0 0 0 FILTER_CNT PMC MMC
C1 0000 CMP2
CMP2_
CR1
0 0 0 0 0 0 0 0SEWE0
PMODE
INV COS OPE EN
C2 0000 CMP2
CMP2_
FPR
0 0 0 0 0 0 0 0 FILT_PER
C3 0000 CMP2
CMP2_
SCR
0 0 0 0 0 0 0 0 0 0 0IERIEFCFRCFF
COUT
C4–DF — CMP2 Reserved RESERVED
E0 0000 PIT PIT_CTRL
0 0 0 0 0 0 0 0 0 PRESCALER PRF PRIE
CNT_EN
E1 0000 PIT PIT_MOD MODULO_VALUE
E2 0000 PIT PIT_CNTR COUNTER_VALUE
E3–FF — PIT Reserved RESERVED
00 0000 PDB PDB_SCR PRESCALER
0AOS0BOS
CONT
SWTRIG
TRIGSEL ENA ENB
01 0000 PDB
PDB_
DELAYA
DELAYA
Table 44. Detailed Peripheral Memory Map (continued)
Offset
Addr.
(Hex)
Reset
Value
(Hex)
Periph. Register
Bit
15
1413121110987654321
Bit
0