Datasheet

Peripheral Register Memory Map and Reset Value
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor 105
17 — HFM Reserved RESERVED
18 0000 HFM FM_DATA FMDATA
19 — HFM Reserved RESERVED
1A FFFF
4
HFM FM_OPT0 IFR_OPT0
1B FFFF
5
HFM FM_OPT1 IFR_OPT1
1D FFFF
6
HFM
FM_
TSTSIG
TST_AREA_SIG
1E–3F — HFM Reserved
RESERVED
1
The binary reset value of this register is 0000 0000 0UUU UUUU, where U represents an undefined value. Spaces have been added to the value for clarity.
2
The binary reset value of this register is 0000 0000 111NC NC NC NC NC. Spaces have been added to the value for clarity.
3
The binary reset value of this register is FS00 0000 0000 0000, where F indicates that the reset state is loaded from the flash array during reset, and where S
indicates that the reset state is determined by the security state of the module. Spaces have been added to the value for clarity.
4
The reset state is loaded from the flash array during reset.
5
The reset state is loaded from the flash array during reset.
6
The reset state is loaded from the flash array during reset.
Table 44. Detailed Peripheral Memory Map (continued)
Offset
Addr.
(Hex)
Reset
Value
(Hex)
Periph. Register
Bit
15
1413121110987654321
Bit
0