Datasheet
Signal/Connection Descriptions
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor 11
3.4 Product Documentation
The documents listed in Table 2 are required for a complete description and proper design with the 56F8006/56F8002.
Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature
Distribution Centers, or online at http://www.freescale.com.
4 Signal/Connection Descriptions
4.1 Introduction
The input and output signals of the 56F8006/56F8002 are organized into functional groups, as detailed in Table 3. Table 4
summarizes all device pins. In Table 4, each table row describes the signal or signals present on a pin, sorted by pin number.
Table 2. 56F8006/56F8002 Device Documentation
Topic Description Order Number
DSP56800E Reference
Manual
Detailed description of the 56800E family architecture,
16-bit digital signal controller core processor, and the
instruction set
DSP56800ERM
56F800x Peripheral
Reference Manual
Detailed description of peripherals of the 56F8006 and
56F8002 devices
MC56F8006RM
56F80x Serial Bootloader
User Guide
Detailed description of the Serial Bootloader in the
56F800x family of devices
TBD
56F8006/56F8002
Technical Data Sheet
Electrical and timing specifications, pin descriptions, and
package descriptions (this document)
MC56F8006
56F8006/56F8002 Errata Details any chip issues that might be present MC56F8006E
Table 3. Functional Group Pin Allocations
Functional Group
Number of Pins
in 28 SOIC
Number of Pins
in 32 LQFP
Number of Pins
in 32 PSDIP
Number of Pins
in 48 LQFP
Power Inputs (V
DD
, V
DDA
) 2224
Ground (V
SS
, V
SSA
) 3334
Reset
1
1
Pins may be shared with other peripherals. See Ta b le 4 .
1111
Pulse Width Modulator (PWM) Ports
1
10 12 12 12
Serial Peripheral Interface (SPI) Ports
1
5777
Serial Communications Interface 0 (SCI) Ports
1
4555
Inter-Integrated Circuit Interface (I
2
C) Ports
1
6777
Analog-to-Digital Converter (ADC) Inputs
1
16 18 18 24
High Speed Analog Comparator Inputs
1
13 15 15 25
Programmable Gain Amplifiers (PGA)
1
4444
Dual Timer Module (TMR) Ports
1
8 101010
Programmable Delay Block (PDB)
1
——— 1
Clock
1
5555
JTAG/Enhanced On-Chip Emulation (EOnCE
1
)4444