Datasheet

MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Signal/Connection Descriptions
Freescale Semiconductor12
In Table 4, peripheral pins in bold identify reset state.
Table 4. 56F8006/56F8002 Pins
Pin Number
Pin Name
Peripherals
28
SOIC
32
LQFP
32
PSDIP
48
LQFP
GPIO I
2
C SCI SPI ADC PGA COMP
Dual
Timer
PWM
Power
and
Ground
JTAG Misc.
261291GPIOB6/RXD/SDA/ANA13
and CMP0_P2/CLKIN
B6 SDA RXD ANA13
1
CMP0_P2 CLKIN
272302GPIOB1/SS
/SDA/ANA12
andCMP2_P3
B1 SDA SS ANA12
1
CMP2_P3
3313GPIOB7/TXD/SCL/ANA11
and CMP2_M3
B7 SCL TXD ANA11
1
CMP2_M3
4324GPIOB5/T1/FAULT3/SCLK B5 SCLK T1 FAULT3
5GPIOE0E0
6GPIOE1/ANB9 and
CMP0_P1
E1 ANB9
1
CMP0_P1
28 5 1 7 ANB8 and PGA1+ and
CMP0_M2/GPIOC4
C4 ANB8
1
PGA1+ CMP0_M2
8GPIOE2/ANB7 and
CMP0_M1
E2 ANB7
1
CMP0_M1
1 6 2 9 ANB6 and PGA1– and
CMP0_P4/GPIOC5
C5 ANB6
1
PGA1– CMP0_P4
10 GPIOC7/ANB5 and
CMP1_M2
C7 ANB5
1
CMP1_M2
2 7 3 11 ANB4 and
CMP1_P1/GPIOC6/PWM2
C6 ANB4
1
CMP1_P1 PWM2
38 412 V
DDA
V
DDA
49 513 V
SSA
V
SSA
14 GPIOE3/ANA10 and
CMP2_M1
E3 ANA10
1
CMP2_M1
5 10 6 15 ANA9 and PGA0– and
CMP2_P4/GPIOC2
C2 ANA9
1
PGA0– CMP2_P4
16 GPIOE5/ANA8 and
CMP2_P1
E5 ANA8
1
CMP2_P1
6 11 7 17 ANA7 and PGA0+ and
CMP2_M2/GPIOC1
C1 ANA7
1
PGA0+ CMP2_M2
18 GPIOE4/ANA6 and
CMP2_P2
E4 ANA6
1
CMP2_P2
7 12 8 19 ANA5 and
CMP1_M1/GPIOC0/FAULT0
C0 ANA5
1
CMP1_M1 FAULT0
813 9 20 V
SS
V
SS
21 V
DD
V
DD
9141022 TCK/GPIOD2/ANA4 and
CMP1_P2/CMP2_OUT
D2 ANA4
1
CMP1_P2,
CMP2_OUT
TCK
10 15 11 23 RESET
/GPIOA7 A7 RESET
11 16 12 24 GPIOB3/MOSI/TIN3/ANA3
and
ANB3/PWM5/CMP1_OUT
B3 MOSI ANA3
1
and
ANB3
1
CMP1_OUT TIN3 PWM5
17 13 25 GPIOB2/MISO/TIN2/ANA2
and ANB2/CMP0_OUT
B2 MISO ANA2
and
ANB2
CMP0_OUT TIN2
12 18 14 26 GPIOA6/FAULT0/ANA1 and
ANB1/SCL/TXD/CLKO_1
A6 SCL TXD ANA1
and
ANB1
FAULT0 CLKO_1
13 19 15 27 GPIOB4/T0/CLKO_0/MISO/
SDA/RXD/ANA0 and ANB0
B4 SDA RXD MISO ANA0
and
ANB0
T0 CLKO_0