Datasheet

MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Signal/Connection Descriptions
Freescale Semiconductor20
GPIOA6
(FAULT0)
(ANA1 &
ANB1)
(SCL)
(TXD)
(CLKO_1)
12 18 14 26 Input/
Output
Input
Analog
Input
Input/Open-
drain
Output
Output
Output
Input,
internal
pullup
enabled
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin.
FAULT0 — PWM fault input 0 used for disabling selected PWM
outputs in cases where fault conditions originate off-chip.
ANA1 and ANB1 — Analog input to channel 1 of ADCA and ADCB.
SCL — The I
2
C serial clock
TXD — The SCI transmit data output or transmit/receive in single
wire operation.
CLKO_1 — This is a buffered clock output; the clock source is
selected by clockout select (CLKOSEL) bits in the clock output
select register (CLKOUT) in the SIM.
When used as an analog input, the signal goes to the ANA1 and
ANB1.
After reset, the default state is GPIOA6.
GPIOB0
(SCLK)
(SCL)
(ANB13)
(PWM3)
(T1)
15 21 17 32 Input/
Output
Input/
Output
Input/Open-
drain
Output
Analog
Input
Output
Input/
Output
Input,
internal
pullup
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
SCLK — The SPI serial clock. In master mode, this pin serves as
an output, clocking slaved listeners. In slave mode, this pin serves
as the data clock input.
SCL — The I
2
C serial clock.
ANB13 — Analog input to channel 13 of ADCB
PWM3 — The PWM channel 3.
T1 — Dual timer module channel 1 input/output.
After reset, the default state is GPIOB0.
Table 5. 56F8006/56F8002 Signal and Package Information (continued)
Signal
Name
28
SOIC
32
LQFP
32
PSDI
P
48
LQFP
Type
State
During
Reset
Signal Description