Datasheet

Memory Maps
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor 33
5.6 EOnCE Memory Map
Control registers of the EOnCE are located at the top of data memory space. These locations are fixed by the 56F800E core.
These registers can also be accessed through JTAG port if flash security is not set. Table 11 lists all EOnCE registers necessary
to access or control the EOnCE.
Table 11. EOnCE Memory Map
Address Register Acronym Register Name
X:0xFF FFFF OTX1/ORX1 Transmit Register Upper Word
Receive Register Upper Word
X:0xFF FFFE OTX/ORX
(32 bits)
Transmit Register
Receive Register
X:0xFF FFFD OTXRXSR Transmit and Receive Status and Control Register
X:0xFF FFFC OCLSR Core Lock/Unlock Status Register
X:0xFF FFFB–
X:0xFF FFA1
Reserved
X:0xFF FFA0 OCR Control Register
X:0xFF FF9F–
X:0xFF FF9E
OSCNTR
(24 bits)
Instruction Step Counter
X:0xFF FF9D OSR Status Register
X:0xFF FF9C OBASE Peripheral Base Address Register
X:0xFF FF9B OTBCR Trace Buffer Control Register
X:0xFF FF9A OTBPR Trace Buffer Pointer Register
X:0xFF FF99–
X:0xFF FF98
OTB
(21–24 bits/stage)
Trace Buffer Register Stages
X:0xFF FF97–
X:0xFF FF96
OBCR
(24 bits)
Breakpoint Unit Control Register
X:0xFF FF95–
X:0xFF FF94
OBAR1
(24 bits)
Breakpoint Unit Address Register 1
X:0xFF FF93–
X:0xFF FF92
OBAR2 (32 bits) Breakpoint Unit Address Register 2
X:0xFF FF91–
X:0xFF FF90
OBMSK (32 bits) Breakpoint Unit Mask Register 2
X:0xFF FF8F Reserved
X:0xFF FF8E OBCNTR EOnCE Breakpoint Unit Counter
X:0xFF FF8D Reserved
X:0xFF FF8C Reserved
X:0xFF FF8B Reserved
X:0xFF FF8A OESCR External Signal Control Register
X:0xFF FF89 –
X:0xFF FF00
Reserved