Datasheet

MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Specifications
Freescale Semiconductor54
8.9 Phase Locked Loop Timing
8.10 Relaxation Oscillator Timing
Table 25. Phase Locked Loop Timing
Characteristic Symbol Min Typ Max Unit
PLL input reference frequency
1
1
An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The
PLL is optimized for 8 MHz input.
f
ref
48— MHz
PLL output frequency
2
2
The core system clock operates at 1/6 of the PLL output frequency.
f
op
120 192 — MHz
PLL lock time
3 4
3
This is the time required after the PLL is enabled to ensure reliable operation.
4
From powerdown to powerup state at 32 MHz system clock state.
t
plls
—40100µs
Accumulated jitter using an 8 MHz external crystal as the PLL source
5
5
This is measured on the CLKO signal (programmed as system clock) over 264 system clocks at 32 MHz system clock
frequency and using an 8 MHz oscillator frequency.
J
A
— — 0.37 %
Cycle-to-cycle jitter t
jitterpll
—350— ps
Table 26. Relaxation Oscillator Timing
Characteristic Symbol Minimum Typical Maximum Unit
Relaxation oscillator output frequency
1
Normal Mode
Standby Mode
1
Output frequency after factory trim.
f
op
—
8.05
400
—
MHz
kHz
Relaxation oscillator stabilization time
2
2
This is the time required from standby to normal mode transition.
t
roscs
—1 3 ms
Cycle-to-cycle jitter. This is measured on the CLKO signal
(programmed prescaler_clock) over 264 clocks
3
3
J
A
is required to meet QSCI requirements.
t
jitterrosc
—400 — ps
Variation over temperature –40 C to 105 C
4
4
See Figure 22. The power supply VDD must be greater than or equal to 2.6 V. Below 2.6 V, the maximum variation
over the whole temperature and whole voltage range from 1.8 V to 2.6 V will be +/-16%.
— — –3.0 to +2.0 %
Variation over temperature 0 C to 105 C
5
5
This data is only applied to devices with temperature range from –40 C to 105 C.
— — –2.0 to +2.0 %
Variation over temperature –40 C to 125 C
4
— — –3.5 to +3.0 %