Datasheet

MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Specifications
Freescale Semiconductor56
8.11 Reset, Stop, Wait, Mode Select, and Interrupt Timing
NOTE
All address and data buses described here are internal.
Figure 24. GPIO Interrupt Timing (Negative Edge-Sensitive)
8.12 External Oscillator (XOSC) Characteristics
Reference Figure 10, and Figure 11, and Figure 12 for crystal or resonator circuits.
Table 27. Reset, Stop, Wait, Mode Select, and Interrupt Timing
1,2
1
In the formulas, T = system clock cycle and T
osc
= oscillator clock cycle. For an operating frequency of 32 MHz, T = 31.25 ns.
At 4 MHz (used coming out of reset and stop modes), T = 250 ns.
2
Parameters listed are guaranteed by design.
Characteristic Symbol Typical Min Typical Max Unit See Figure
Minimum RESET Assertion Duration t
RA
4T — ns —
Minimum GPIO pin Assertion for Interrupt t
IW
2T — ns Figure 24
RESET
deassertion to First Address Fetch t
RDA
96T
OSC
+ 64T 97T
OSC
+ 65T ns —
Delay from Interrupt Assertion to Fetch of first
instruction (exiting Stop)
t
IF
—6Tns—
GPIO pin
(Input)
t
IW