Datasheet

MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Specifications
Freescale Semiconductor62
Figure 31. RXD Pulse Width
Figure 32. TXD Pulse Width
8.13.3 Inter-Integrated Circuit Interface (I
2
C) Timing
Table 31. I
2
C Timing
Characteristic Symbol
Standard Mode
Unit
Minimum Maximum
SCL Clock Frequency f
SCL
0100 MHz
Hold time (repeated) START condition.
After this period, the first clock pulse is generated.
t
HD; STA
4.0 — s
LOW period of the SCL clock t
LOW
4.7 — s
HIGH period of the SCL clock t
HIGH
4.0 — s
Set-up time for a repeated START condition t
SU; STA
4.7 — s
Data hold time for I
2
C bus devices t
HD; DAT
0
1
1
The master mode I
2
C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, a negative hold time can result, depending on the edge rates of the SDA and SCL lines.
3.45
2
2
The maximum t
HD; DAT
must be met only if the device does not stretch the LOW period (t
LOW
) of the SCL signal.
s
Data set-up time t
SU; DAT
250 — ns
Rise time of SDA and SCL signals t
r
— 1000 ns
Fall time of SDA and SCL signals t
f
—300ns
Set-up time for STOP condition t
SU; STO
4.0 — s
Bus free time between STOP and START condition t
BUF
4.7 — s
Pulse width of spikes that must be suppressed by the input filter t
SP
N/A N/A ns
RXD
PW
RXD
SCI receive
data pin
(Input)
TXD
PW
TXD
SCI receive
data pin
(Input)