Datasheet

MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Specifications
Freescale Semiconductor68
8.17 HSCMP Specifications
8.18 Optimize Power Consumption
See Section 8.6, “Supply Current Characteristics,” for a list of I
DD
requirements for the 56F8006/56F8002. This section
provides additional detail that can be used to optimize power consumption for a given application.
1
Typical values assume V
DDA
= 3.0 V, Temp = 25C, f
ADCK
=1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2
1 LSB = (V
REFH
– V
REFL
)/2
N
3
Monotonicity and no-missing-codes guaranteed in 10-bit and 8-bit modes
4
Based on input pad leakage current. Refer to pad electricals.
Table 38. HSCMP Specifications
Parameter Symbol Min Typ Max Unit
Supply voltage V
PWR
1.8 3.6 V
Supply current, high speed mode (EN=1,
PMODE=1, V
DDA
 V
LVI_trip
)
I
DDAHS
150 A
Supply current, low speed mode (EN=1,
PMODE=0)
I
DDALS
10 A
Supply current, off mode (EN=0,) I
DDAOFF
100 nA
Analog input voltage V
AIN
V
SSA
– 0.01 V
DDA
+ 0.01 V
Analog input offset voltage V
AIO
40 mV
Analog comparator hysteresis V
H
3.0 20.0 mV
Propagation Delay, high speed mode (EN=1,
PMODE=1), 2.4 V < V
DDA
< 3.6 V
t
DHSN
1
1
Measured with an input waveform that switches 30 mV above and below the reference, to the CMPO output pin. V
DDA
>
V
LVI_WARNING
=> LVI_WARNING NOT ASSERTED.
70 140 ns
Propagation Delay, High Speed Mode (EN=1,
PMODE=1), 1.8 V < V
DDA
< 2.4 V
t
DHSB
2
2
Measured with an input waveform that switches 30mV above and below the reference, to the CMPO output pin. V
DDA
<
V
LVI_WARNING
=> LVI_WARNING ASSERTED.
70 249 ns
Propagation Delay, Low Speed Mode (EN=1,
PMODE=0), 2.4 V < V
DDA
< 3.6 V
t
AINIT
3
3
Measured with an input waveform that switches 30mV above and below the reference, to the CMPO output pin. V
DDA
>
V
LVI_WARNING
=> LVI_WARNING NOT ASSERTED.
400 600 ns
Propagation Delay, Low Speed Mode (EN=1,
PMODE=0), 1.8 V < V
DDA
< 2.4 V
t
AINIT
4
4
Measured with an input waveform that switches 30mV above and below the reference, to the CMPO output pin. V
DDA
<
V
LVI_WARNING
=> LVI_WARNING ASSERTED.
400 600 ns