Datasheet

Design Considerations
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor 71
junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects
of the thermocouple wire.
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case
of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of
the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to
the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature
and then back-calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this
case temperature, the junction temperature is determined from the junction-to-case thermal resistance.
9.2 Electrical Design Considerations
CAUTION
This device contains protective circuitry to guard against damage due to high static voltage
or electrical fields. However, take normal precautions to avoid application of any voltages
higher than maximum-rated voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an appropriate voltage level.
Use the following list of considerations to assure correct operation of the 56F8006/56F8002:
• Provide a low-impedance path from the board power supply to each V
DD
pin on the 56F8006/56F8002 and from the
board ground to each V
SS
(GND) pin.
• The minimum bypass requirement is to place 0.01–0.1µF capacitors positioned as near as possible to the package
supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the V
DD
/V
SS
pairs,
including V
DDA
/V
SSA.
Ceramic and tantalum capacitors tend to provide better tolerances.
• Ensure that capacitor leads and associated printed circuit traces that connect to the chip V
DD
and V
SS
(GND) pins are
as short as possible.
• Bypass the V
DD
and V
SS
with approximately 100 µF, plus the number of 0.1 µF ceramic capacitors.
• PCB trace lengths should be minimal for high-frequency signals.
• Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is
especially critical in systems with higher capacitive loads that could create higher transient currents in the V
DD
and
V
SS
circuits.
• Take special care to minimize noise levels on the V
REF
, V
DDA
, and V
SSA
pins.
• Using separate power planes for V
DD
and V
DDA
and separate ground planes for V
SS
and V
SSA
are recommended.
Connect the separate analog and digital power and ground planes as near as possible to power supply outputs. If an
analog circuit and digital circuit are powered by the same power supply, you should connect a small inductor or ferrite
bead in serial with V
DDA
and V
SSA
traces.
• Physically separate analog components from noisy digital components by ground planes. Do not place an analog trace
in parallel with digital traces. Place an analog ground trace around an analog signal trace to isolate it from digital traces.
• Because the flash memory is programmed through the JTAG/EOnCE port, SPI, SCI, or I
2
C, the designer should
provide an interface to this port if in-circuit flash programming is desired.
• If desired, connect an external RC circuit to the RESET
pin. The resistor value should be in the range of 4.7 k–10 k;
the capacitor value should be in the range of 0.22 µF–4.7 µF.
• Configuring the RESET
pin to GPIO output in normal operation in a high-noise environment may help to improve the
performance of noise transient immunity.
• Add a 2.2 k external pullup on the TMS pin of the JTAG port to keep EOnCE in a restate during normal operation if
JTAG converter is not present.
• During reset and after reset but before I/O initialization, all I/O pins are at input state with internal pullup enabled. The
typical value of internal pullup is around 33 k. These internal pullups can be disabled by software.
• To eliminate PCB trace impedance effect, each ADC input should have a no less than 33 pF 10  RC filter.
• External clamp diodes on analog input pins are recommended.