Datasheet

Interrupt Vector Table
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor 85
Reserved 34- 39 0x22-0x27 0 P:0x44 -
P:0x4E
Reserved
core 40
N/A 0 P:0x50 SW Interrupt 0
core 41
N/A 1 P:0x52 SW Interrupt 1
core 42
N/A 2 P:0x54 SW Interrupt 2
core 43
N/A 3 P:0x56 SW Interrupt 3
SWILP 44
N/A -1 P:0x58 SW Interrupt Low Priority
USER1 45
N/A 1 P:0x5A User Programmable Priority Level 1 Interrupt
USER2 46
N/A 1 P:0x5C User Programmable Priority Level 1 Interrupt
USER3 47
N/A 1 P:0x5E User Programmable Priority Level 1 Interrupt
USER4 48
N/A 2 P:0x60 User Programmable Priority Level 2 Interrupt
USER5 49
N/A 2 P:0x62 User Programmable Priority Level 2 Interrupt
USER6
3
50 N/A 2 P:0x64 User Programmable Priority Level 2 Interrupt
1
Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced from
the vector table, providing only 19 bits of address.
2
If the VBA is set to the reset value, the first two locations of the vector table overlay the chip reset addresses because the
reset address would match the base of this vector table.
3
USER6 vector can be defined as a fast interrupt if the instruction located in this vector location is not a JSR or BSR instruction.
Please see section 9.3.3.3 of DSP56800E 16-Bit Core Reference Manual for detail.
Table 43. Interrupt Vector Table Contents
1
(continued)
Peripheral
Vector
Number
User
Encoding
Priority
Level
Vector Base
Address +
Interrupt Function