Datasheet

Peripheral Register Memory Map and Reset Value
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor 86
Appendix B
Peripheral Register Memory Map and Reset Value
NOTE
In Table 44, ADC0 stands for ADCA, ADC1 stands for ADCB, and GPIOn is the same as GPIO_n (for example,
GPIOA_PUR is the same as GPIO_A_PUR).
Table 44. Detailed Peripheral Memory Map
Offset
Addr.
(Hex)
Reset
Value
(Hex)
Periph. Register
Bit
15
1413121110987654321
Bit
0
00 0000 TMR0
TMR0_
COMP1
COMPARISON_1
01 0000 TMR0
TMR0_
COMP2
COMPARISON_2
02 0000 TMR0
TMR0_
CAPT
CAPTURE
03 0000 TMR0
TMR0_
LOAD
LOAD
04 0000 TMR0
TMR0_
HOLD
HOLD
05 0000 TMR0
TMR0_
CNTR
COUNTER
06 0000 TMR0
TMR0_
CTRL
CM PCS SCS
ONCE
LENGTH
DIR
Co_INIT
OM
07 0000 TMR0
TMR0_
SCTRL
TCF
TCFIE
TOF
TOFIE
IEF IEFIE IPS
INPUT
CAPTURE_
MODE
MSTR
EEOF
VAL
FORCE
OPS OEN
08 0000 TMR0
TMR0_
CMPLD1
COMPARATOR_LOAD_1
09 0000 TMR0
TMR0_
CMPLD2
COMPARATOR_LOAD_2