Datasheet

Peripheral Register Memory Map and Reset Value
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor 87
0A 0000 TMR0
TMR0_
CSCTRL
DBG_EN
FAULT
ALT_LOAD
0 0 0 0
TCF2EN
TCF1EN
TCF2 TCF1 CL2 CL1
0B 0000 TMR0
TMR0_
FILT
0 0 0 0 0 FILT_CNT FILT_PER
0C–0E — TMR0 Reserved
RESERVED
0F 000F TMR0
TMR_
ENBL
0 0 0 0 0 0 0 0 0 0 0 0ENBL
10 0000 TMR1
TMR1_
COMP1
COMPARISON_1
11 0000 TMR1
TMR1_
COMP2
COMPARISON_2
12 0000 TMR1
TMR1_
CAPT
CAPTURE
13 0000 TMR1
TMR1_
LOAD
LOAD
14 0000 TMR1
TMR1_
HOLD
HOLD
15 0000 TMR1
TMR1_
CNTR
COUNTER
16 0000 TMR1
TMR1_
CTRL
CM PCS SCS
ONCE
LENGTH
DIR
COINIT
OM
17 0000 TMR1
TMR1_
SCTRL
TCF
TCFIE
TOF
TOFIE
IEF IEFIE IPS
INPUT
CAPTURE_
MODE
MSTR
EEOF
VAL
FORCE
OPS OEN
18 0000 TMR1
TMR1_
CMPLD1
COMPARATOR_LOAD_1
19 0000 TMR1
TMR1_
CMPLD2
COMPARATOR_LOAD_2
Table 44. Detailed Peripheral Memory Map (continued)
Offset
Addr.
(Hex)
Reset
Value
(Hex)
Periph. Register
Bit
15
1413121110987654321
Bit
0