Datasheet

Peripheral Register Memory Map and Reset Value
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor 91
61 0000 ADC0
ADC0_
ADCSC2
0 0 0 0 0 0 0 0
ADACT
ADTRG
0 0 0 ECC REFSEL
62–65 — ADC0 Reserved
RESERVED
66 0000 ADC0
ADC0_
ADCCFG
0 0 0 0 0 0 0 0
ADLPC
ADIV
ADLSMP
MODE ADICLK
67–69 — ADC0 Reserved
RESERVED
6A 001F ADC0
ADC0_
ADCSC1B
0 0 0 0 0 0 0 0
COCO
AIEN
ADCO
ADCH
6B 0000 ADC0
ADC0_
ADCRA
0
ADR11 ADR10
ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
0 0 0
6C 0000 ADC0
ADC0_
ADCRB
0
ADR11 ADR10
ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
0 0 0
6D–6F — ADC0 Reserved
RESERVED
80 001F ADC1
ADC1_
ADCSC1A
0 0 0 0 0 0 0 0
COCO
AIEN
ADCO
ADCH
81 0000 ADC1
ADC1_
ADCSC2
0 0 0 0 0 0 0 0
ADACT
ADTRG
0 0 0 ECC REFSEL
82–85 — ADC1 Reserved
RESERVED
86 0000 ADC1
ADC1_
ADCCFG
0 0 0 0 0 0 0 0
ADLPC
ADIV
ADLSMP
MODE ADICLK
87–89 — ADC1 Reserved
RESERVED
8A 001F ADC1
ADC1_
ADCSC1B
0 0 0 0 0 0 0 0
COCO
AIEN
ADCO
ADCH
Table 44. Detailed Peripheral Memory Map (continued)
Offset
Addr.
(Hex)
Reset
Value
(Hex)
Periph. Register
Bit
15
1413121110987654321
Bit
0