Datasheet

Peripheral Register Memory Map and Reset Value
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor 95
60 0011 OCCS
OCCS_
CTRL
PLLIE1 PLLIE0
LOCIE
0 0 0
LCKON
0 0
PLLPD
0
PRECS
ZSRC
61 2000 OCCS
OCCS_
DIVBY
LORTP COD
0 0 0 0 0 0 0 0
62 0015 OCCS
OCCS_
STAT
LOLI1 LOLI0
LOCI 0 0 0 0 0 0LCK1LCK0
PLLPDN
0
COSC_RDY
ZSRC
64 1611 OCCS
OCCS_
OCTRL
ROPD
ROSB
COHL
CLK_MODE
RANGE
EXT_SEL
TRIM
65 0000 OCCS
OCCS_
CLKCHKR
CHK_ENA
REFERENCE_CNT
66 0000 OCCS
OCCS_
CLKCHKT
0 0 0 0 0 0 0 0 0 TARGET_CNT
67 0000 OCCS
OCCS_
PROT
0 0 0 0 0 0 0 0 0 0 FRQEP OSCEP PLLEP
68–7F — OCCS Reserved
RESERVED
80 00FF GPIOA
GPIOA_
PUR
0 0 0 0 0 0 0 0PU
81 0000 GPIOA GPIOA_DR
0 0 0 0 0 0 0 0D
82 0000 GPIOA
GPIOA_
DDR
0 0 0 0 0 0 0 0DD
83 0080 GPIOA
GPIOA_
PER
0 0 0 0 0 0 0 0PE
84 — GPIOA Reserved
RESERVED
Table 44. Detailed Peripheral Memory Map (continued)
Offset
Addr.
(Hex)
Reset
Value
(Hex)
Periph. Register
Bit
15
1413121110987654321
Bit
0