Datasheet

MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor96
Peripheral Register Memory Map and Reset Value
85 0000 GPIOA
GPIOA_
IENR
0 0 0 0 0 0 0 0IEN
86 0000 GPIOA
GPIOA_
IPOLR
0 0 0 0 0 0 0 0IPOL
87 0000 GPIOA
GPIOA_
IPR
0 0 0 0 0 0 0 0IP
88 0000 GPIOA
GPIOA_
IESR
0 0 0 0 0 0 0 0IES
89 — GPIOA Reserved
RESERVED
8A 0000 GPIOA
GPIOA_
RAWDATA
0 0 0 0 0 0 0 0RAWDATA
8B 0000 GPIOA
GPIOA_
DRIVE
0 0 0 0 0 0 0 0DRIVE
8C 00FF GPIOA GPIOA_IFE
0 0 0 0 0 0 0 0IFE
8D 0000 GPIOA
GPIOA_
SLEW
0 0 0 0 0 0 0 0SLEW
8E–9F — GPIOA Reserved
RESERVED
A0 00FF GPIOB
GPIOB_
PUR
0 0 0 0 0 0 0 0PUR
A1 0000 GPIOB GPIOB_DR
0 0 0 0 0 0 0 0DR
A2 0000 GPIOB
GPIOB_
DDR
0 0 0 0 0 0 0 0 DDR
A3 0080 GPIOB
GPIOB_
PER
0 0 0 0 0 0 0 0 PER
A4 — GPIOB Reserved
RESERVED
A5 0000 GPIOB
GPIOB_
IENR
0 0 0 0 0 0 0 0IENR
A6 0000 GPIOB
GPIOB_
IPOLR
0 0 0 0 0 0 0 0IPOLR
Table 44. Detailed Peripheral Memory Map (continued)
Offset
Addr.
(Hex)
Reset
Value
(Hex)
Periph. Register
Bit
15
1413121110987654321
Bit
0