56F8014 Data Sheet Technical Data 56F8000 16-bit Digital Signal Controllers MC56F8014 Rev. 11 05/2008 freescale.
Document Revision History Version History Description of Change Rev 0 Initial release Rev 1 Updates to Part 10, Specifications, Table 10-1, added maximum clamp current, per pin Table 10-11, clarified variation over temperature table and graph Table 10-15, added LIN slave timing Rev 2 Added alternate pins to Figure 11-1 and Table 11-1. Rev 3 Corrected bit selects in Timer Channel 3 Input (TC3_INP) bit 9, Section 6.3.1.7, clarified Section 1.4.
Document Revision History (Continued) Version History Description of Change Rev. 9 Added the following note to the description of the TMS signal in Table 2-3: Note: Always tie the TMS pin to VDD through a 2.2K resistor. Rev. 10 • In Table 2-3, changed VCAP value from 4.7 μF to 2.2 μF. • In Table 2-3, changed the input type for FAULT3 (was “Output”, is “Input”). • In Table 2-3, changed the input type for FAULT2 (was “Input/Output”, is “Input”). • Revised Section 7, Security Features.
56F8014 General Description • Up to 32 MIPS at 32MHz core frequency • One Inter-Integrated Circuit (I2C) Port • DSP and MCU functionality in a unified, C-efficient architecture • Computer Operating Properly (COP)/Watchdog • On-Chip Relaxation Oscillator • 16KB Program Flash • Integrated Power-On Reset and Low-Voltage Interrupt Module • 4KB Unified Data/Program RAM • One 5-channel PWM module • JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging • Two 4-channel 12-bit ADCs •
6F8014 Data Sheet Table of Contents Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 6 1.1. 1.2. 1.3. 1.4. 1.5. 1.6. 1.7. 1.8. 56F8014 Features . . . . . . . . . . . . . . . . . . . . 6 56F8014 Description. . . . . . . . . . . . . . . . . . . 8 Award-Winning Development Environment . 8 Architecture Block Diagram . . . . . . . . . . . . . 9 Synchronize ADC with PWM . . . . . . . . . . . . 9 Multiple Frequency PWM Output . . . . . . . . . 9 Product Documentation . . . . . . . . . . . . . . .
Part 1 Overview 1.1 56F8014 Features 1.1.1 • • • • • • • • • • • • • • 1.1.
56F8014 Features • • • • • • • • • • — Each complementary PWM signal pair can output a different switching frequency by selecting PWM generation sources from: – PWM generator – External GPIO – Internal timers – ADC conversion result of over/under limits: When conversion result is greater than high limit, deactivate PWM signal When conversion result is less than low limit, activate PWM signal Two independent 12-bit Analog-to-Digital Converters (ADCs) — 2 x 4 channel inputs — Supports both simultaneous
• • 1.1.4 • • • • • — External clock source On-chip regulators for digital and analog circuitry to lower cost and reduce noise JTAG/EOnCE debug programming interface for real-time debugging Energy Information Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs On-chip regulators for digital and analog circuitry to lower cost and reduce noise Wait and Stop modes available ADC smart power management Each peripheral can be individually disabled to save power 1.
Architecture Block Diagram create a complete, scalable tools solution for easy, fast, and efficient development. 1.4 Architecture Block Diagram The 56F8014’s architecture is shown in Figure 1-1, Figure 1-2, and Figure 1-3. Figure 1-1 illustrates how the 56800E system buses communicate with internal memories and the IPBus Bridge, as well as showing the internal connections between each unit of the 56800E core. Figure 1-2 shows the peripherals and control blocks connected to the IPBus Bridge.
— Signal of over/under limit of ADC sample 2 can be used to drive PWM 4 and 5 DSP56800E Core Program Control Unit PC LA LA2 HWS0 HWS1 FIRA OMR SR LC LC2 FISR Address Generation Unit (AGU) Instruction Decoder Interrupt Unit ALU1 ALU2 R0 R1 R2 R3 R4 R5 N M01 N3 Looping Unit Program Memory SP XAB1 XAB2 PAB PDB Data / Program RAM CDBW CDBR XDB2 A2 B2 C2 D2 BitManipulation Unit Enhanced OnCE™ JTAG TAP Y A1 B1 C1 D1 Y1 Y0 X0 MAC and ALU A0 B0 C0 D0 IPBUS Interface Data Arithmetic Logic Unit
Multiple Frequency PWM Output To/From IPBus Bridge CLKGEN (ROSC / PLL / CLKIN) GPIOAn GPIOBn 8 8 GPIOCn 6 GPIODn 4 Interrupt Controller Low-Voltage Interrupt GPIO A POR & LVI GPIO B System POR GPIO C SIM RESET / GPIOA7 GPIO D COP Reset COP IPBus (Continues on Figure 1-3) Figure 1-2 Peripheral Subsystem 56F8014 Technical Data, Rev.
(Continued from Figure 1-2) To/From IPBus Bridge 2 PWM4, 5 PWM PWM0 - 3 4 PWM0 - 3 GPIOA0 - 3 2 Fault1, 2 PWM4, 5 Fault0 Output Controls Reload Pulse 3 Fault1, 2 Fault3 T2, 3 2 2 Fault0 from ADC T3i GPIOA4 - 5 GPIOA6 Fault3 T2/3 2 T1 GPIOB5 T1 Timer T2o, T3o T0 T0 I2C is muxed with both SPI and SCI. T2 and T3 are muxed with SPI and PWM.
Product Documentation 1.7 Product Documentation The documents listed in Table 1-1 are required for a complete description and proper design with the 56F8014. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, or online at: http://www.freescale.
Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F8014 are organized into functional groups, as detailed in Table 2-1. Table 2-2 summarizes all device pins. In Table 2-2, each table row describes the signal or signals present on a pin, sorted by pin number.
Introduction Table 2-2 56F8014 Pins Peripherals: LQFP Pin # Pin Name Signal Name GPIO I2C SCI SPI ADC PWM Quad Power & Timer Ground 1 GPIOB1 GPIOB1, SS, SDA B1 SDA 2 GPIOB7 GPIOB7, TXD, SCL B7 SCL 3 GPIOB5 GPIOB5, T1, FAULT3 B5 4 ANB0 ANB0, GPIOC4 C4 ANB0 5 ANB1 ANB1, GPIOC5 C5 ANB1 6 ANB2 ANB2, VREFL, GPIOC6 C6 ANB2, VREFL 7 ANB3 ANB3, GPIOC7 C7 ANB3 8 VDDA VDDA VDDA 9 VSSA VSSA VSSA 10 ANA3 ANA3, GPIOC3 C3 ANA3 11 ANA2 ANA2, VREFH, GPIOC2 C2 ANA2,
Table 2-2 56F8014 Pins (Continued) Peripherals: LQFP Pin # Pin Name Signal Name GPIO I2C SCI SPI ADC PWM Quad Power & Timer Ground JTAG 25 VDD_IO VDD_IO VDD_IO 26 VSS_IO VSS_IO 27 GPIOA1 GPIOA1, PWM1 A1 PWM1 28 GPIOA0 GPIOA0, PWM0 A0 PWM0 29 TDI TDI, GPIOD0 D0 TDI 30 TMS TMS, GPIOD3 D3 TMS 31 TDO TDO, GPIOD1 D1 TDO 32 GPIOB6 GPIOB6, RXD, SDA, CLKIN B6 VSS_IO SDA RXD Misc. CLKIN 56F8014 Technical Data, Rev.
Introduction VDD_IO Power VSS_IO Ground VDDA Power VSSA Ground 1 2 1 1 56F8014 Other Supply Ports VCAP 1 GPIOB0 (SCLK, SCL) GPIOB1 (SS, SDA) 1 1 GPIOB2 (MISO, T2) SPI Port or I2C Port or Timer Port or GPIO 1 GPIOB3 (MOSI, T3) 1 SCI Port or I2C Port or GPIO GPIOB6 (RXD, SDA, CLKIN) 1 GPIOB7 (TXD, SCL) GPIOA0 - 2 (PWM0 - 2) 3 1 GPIOA4 (PWM4, FAULT1, T2) 1 PWM Port or Timer Port or GPIO GPIOA5 (PWM5, FAULT2, T3) RESET 1 RESET (GPIOA7) 1 2 GPIOB4 (T0, CLKO) Timer Port or GPIO 1 1 A
2.2 56F8014 Signal Pins After reset, each pin is configured for its primary function (listed first). Any alternate functionality must be programmed. Table 2-3 56F8014 Signal and Package Information for the 32-Pin LQFP Signal Name LQFP Pin No. Type State During Reset Signal Description VDD_IO 25 Supply Supply I/O Power — This pin supplies 3.3V power to the chip I/O interface. VSS_IO 14 Supply Supply VSS — These pins provide ground for chip logic and I/O drivers.
56F8014 Signal Pins Table 2-3 56F8014 Signal and Package Information for the 32-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOB7 2 Type Input/ Output State During Reset Input with internal pull-up enabled Signal Description Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. (TXD) Input/ Output Transmit Data — SCI transmit data output or transmit / receive in single wire opeation. (SCL2) Input/ Output Serial Clock — This pin serves as the I2C serial clock.
Table 2-3 56F8014 Signal and Package Information for the 32-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOB5 3 Type Input/ Output (T1) Input/ Output (FAULT3) Input State During Reset Input with internal pull-up enabled Signal Description Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. T1 — Timer, Channel 1 FAULT3 — This fault input pin is used for disabling selected PWM outputs in cases where fault conditions originate off-chip.
56F8014 Signal Pins Table 2-3 56F8014 Signal and Package Information for the 32-Pin LQFP (Continued) Signal Name LQFP Pin No. Type State During Reset TDO 31 Output Output (GPIOD1) Input/ Output Signal Description Test Data Output — This tri-stateable output pin provides a serial output data stream from the JTAG/EOnCE port. It is driven in the shift-IR and shift-DR controller states, and changes on the falling edge of TCK.
Table 2-3 56F8014 Signal and Package Information for the 32-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOB2 18 Type Input/ Output State During Reset Input with internal pull-up enabled Signal Description Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. (MISO) Input/ Output SPI Master In/Slave Out — This serial data pin is an input to a master device and an output from a slave device.
56F8014 Signal Pins Table 2-3 56F8014 Signal and Package Information for the 32-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOA1 27 (PWM1) Type Input/ Output State During Reset Input with internal pull-up enabled Output Signal Description Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. PWM1 — This is one of the six PWM output pins. After reset, the default state is GPIOA1.
Table 2-3 56F8014 Signal and Package Information for the 32-Pin LQFP (Continued) Signal Name LQFP Pin No. Type ANA0 13 Input (GPIOC0) State During Reset Analog Input Input/ Output Signal Description ANA0 — Analog input to ADC A, channel 0 Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is ANA0.
56F8014 Signal Pins Table 2-3 56F8014 Signal and Package Information for the 32-Pin LQFP (Continued) Signal Name LQFP Pin No. Type ANB1 5 Input (GPIOC5) State During Reset Analog Input Input/ Output Signal Description ANB1 — Analog input to ADC B, channel 1 Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is ANB1.
Part 3 OCCS 3.1 Overview This module provides the system clock, which uses it to generate the various chip clocks. This module also produces the oscillator clock signals, plus the ADC clock and high-speed peripheral clock. The on-chip clock synthesis module allows product design using an internal relaxation oscillator to run 56F801X family parts at user-selectable frequencies up to 32MHz. 3.2 Features The On-Chip Clock Synthesis (OCCS) module interfaces to the oscillator and PLL.
Operating Modes The 56F801X family parts’ on-chip clock synthesis module has the following registers: • • • • • Control Register (OCCS_CR) Divide-by Register (OCCS_DB) Status Register (OCCS_SR) Shutdown Register (OCCS_SHUTDN) Oscillator Control Register (OCCS_OCTRL) For more information on these registers, please refer to the 56F801X Peripheral Reference Manual. 3.3.1 External Clock Source The recommended method of connecting an external clock is illustrated in Figure 3-1.
3.4 Block Diagram Figure 3-2 provides a block diagram which shows how the 56F8014 creates its internal clock, using the relaxation oscillator as an 8MHz clock reference for the PLL.
Pin Descriptions 3.5 Pin Descriptions 3.5.1 External Reference (GPIOB6 / RXD / SDA / CLKIN) After reset, the internal relaxation oscillator is selected as the clock source for the chip. The user then has the option of switching to an external clock reference by enabling the PRECS bit in the OCCS Oscillator Control register, if desired. Part 4 Memory Map 4.1 Introduction The 56F8014 device is a 16-bit motor-control chip based on the 56800E core.
Table 4-2 Interrupt Vector Table Contents1 Peripheral Vector Number Priority Level Vector Base Address + Interrupt Function core P:$00 Reserved for Reset Overlay2 core P:$02 Reserved for COP Reset Overlay core 2 3 P:$04 Illegal Instruction core 3 3 P:$06 SW Interrupt 3 core 4 3 P:$08 HW Stack Overflow core 5 3 P:$0A Misaligned Long Word Access core 6 1-3 P:$0C EOnCE Step Counter core 7 1-3 P:$0E EOnCE Breakpoint Unit 0 core 8 1-3 P:$10 EOnCE Trace Buffer core 9
Program Map Table 4-2 Interrupt Vector Table Contents1 (Continued) Peripheral Vector Number Priority Level Vector Base Address + Interrupt Function Timer 38 0-2 P:$4C Timer Channel 2 Timer 39 0-2 P:$4E Timer Channel 3 ADC 40 0-2 P:$50 ADCA Conversion Complete ADC 41 0-2 P:$52 ADCB Conversion Complete ADC 42 0-2 P:$54 ADC Zero Crossing or Limit Error PWM 43 0-2 P:$56 Reload PWM PWM 44 0-2 P:$58 PWM Fault SWILP 45 -1 P:$5A SW Interrupt Low Priority 1.
4.4 Data Map Table 4-4 Data Memory Map1 Begin/End Address Memory Allocation X:$FF FFFF X:$FF FF00 EOnCE 256 locations allocated X:$FF FEFF X:$01 0000 RESERVED X:$00 FFFF X:$00 F000 On-Chip Peripherals 4096 locations allocated X:$00 EFFF X:$00 8800 RESERVED X:$00 EFFF X:$00 0800 Reserved X:$00 7FFF X:$00 0040 RESERVED X:$00 07FF X:$00 0000 On-Chip Data RAM2 4KB 1. All addresses are 16-bit Word addresses. 2. This RAM is shared with Program space starting at P: $00 8000; see Figure 4-1.
Peripheral Memory Mapped Registers Table 4-5 EOnCE Memory Map Address Register Acronym Register Name X:$FF FFFF OTX1 / ORX1 Transmit Register Upper Word Receive Register Upper Word X:$FF FFFE OTX / ORX (32 bits) Transmit Register Receive Register X:$FF FFFD OTXRXSR Transmit and Receive Status and Control Register X:$FF FFFC OCLSR Core Lock / Unlock Status Register X:$FF FFFB - X:$FF FFA1 X:$FF FFA0 Reserved OCR Control Register X:$FF FF9F Instruction Step Counter X:$FF FF9E OSCNTR (24
The following tables list all of the peripheral registers required to control or access the peripherals.
Peripheral Memory Mapped Registers Table 4-7 Quad Timer Registers Address Map (Continued) (TMR_BASE = $00 F000) Register Acronym Address Offset Register Description TMR1_CAPT $12 Capture Register TMR1_LOAD $13 Load Register TMR1_HOLD $14 Hold Register TMR1_CNTR $15 Counter Register TMR1_CTRL $16 Control Register TMR1_SCTRL $17 Status and Control Register TMR1_CMPLD1 $18 Comparator Load Register 1 TMR1_CMPLD2 $19 Comparator Load Register 2 TMR1_CSCTRL $1A Comparator Status and C
Table 4-8 Pulse Width Modulator Registers Address Map (PWM_BASE = $00 F040) Register Acronym Address Offset Register Description PWM_CTRL $0 Control Register PWM_FCTRL $1 Fault Control Register PWM_FLTACK $2 Fault Status Acknowledge Register PWM_OUT $3 Output Control Register PWM_CNTR $4 Counter Register PWM_CMOD $5 Counter Modulo Register PWM_VAL0 $6 Value Register 0 PWM_VAL1 $7 Value Register 1 PWM_VAL2 $8 Value Register 2 PWM_VAL3 $9 Value Register 3 PWM_VAL4 $A Value R
Peripheral Memory Mapped Registers Table 4-9 Interrupt Control Registers Address Map (Continued) (ITCN_BASE = $00 F060) Register Acronym Address Offset Register Description ITCN_FIM1 $9 Fast Interrupt Match 1 Register ITCN_FIVAL1 $A Fast Interrupt Vector Address Low 1 Register ITCN_FIVAH1 $B Fast Interrupt Vector Address High 1 Register ITCN_IRQP 0 $C IRQ Pending Register 0 ITCN_IRQP 1 $D IRQ Pending Register 1 ITCN_IRQP 2 $E IRQ Pending Register 2 ITCN_ICTRL $12 Reserved Interrupt C
Table 4-10 Analog-to-Digital Converter Registers Address Map (Continued) (ADC_BASE = $00 F080) Register Acronym Address Offset Register Description ADC_LOLIM6 $17 Low Limit Register 6 ADC_LOLIM7 $18 Low Limit Register 7 ADC_HILIM0 $19 High Limit Register 0 ADC_HILIM1 $1A High Limit Register 1 ADC_HILIM2 $1B High Limit Register 2 ADC_HILIM3 $1C High Limit Register 3 ADC_HILIM4 $1D High Limit Register 4 ADC_HILIM5 $1E High Limit Register 5 ADC_HILIM6 $1F High Limit Register 6 ADC
Peripheral Memory Mapped Registers Table 4-12 Serial Peripheral Interface Registers Address Map (SPI_BASE = $00 F0C0) Register Acronym Address Offset Register Description SPI_SCTRL $0 Status and Control Register SPI_DSCTRL $1 Data Size and Control Register SPI_DRCV $2 Data Receive Register SPI_DXMIT $3 Data Transmit Register Table 4-13 I2C Registers Address Map (I2C_BASE = $00 F0D0) Register Acronym Address Offset Register Description I2C_ADDR $0 Address Register I2C_FDIV $1 Frequenc
Table 4-16 GPIOA Registers Address Map (GPIOA_BASE = $00 F100) Register Acronym Address Offset Register Description GPIOA_PUPEN $0 Pull-up Enable Register GPIOA_DATA $1 Data Register GPIOA_DDIR $2 Data Direction Register GPIOA_PEREN $3 Peripheral Enable Register GPIOA_IASSRT $4 Interrupt Assert Register GPIOA_IEN $5 Interrupt Enable Register GPIOA_IEPOL $6 Interrupt Edge Polarity Register GPIOA_IPEND $7 Interrupt Pending Register GPIOA_IEDGE $8 Interrupt Edge-Sensitive Register
Peripheral Memory Mapped Registers Table 4-18 GPIOC Registers Address Map (GPIOC_BASE = $00 F120) Register Acronym Address Offset Register Description GPIOC_PUPEN $0 Pull-up Enable Register GPIOC_DATA $1 Data Register GPIOC_DDIR $2 Data Direction Register GPIOC_PEREN $3 Peripheral Enable Register GPIOC_IASSRT $4 Interrupt Assert Register GPIOC_IEN $5 Interrupt Enable Register GPIOC_IEPOL $6 Interrupt Edge Polarity Register GPIOC_IPEND $7 Interrupt Pending Register GPIOC_IEDGE $8
Table 4-20 System Integration Module Registers Address Map (SIM_BASE = $00 F140) Register Acronym Address Offset Register Description SIM_CTRL $0 Control Register SIM_RSTAT $1 Reset Status Register SIM_SWC0 $2 Software Control Register 0 SIM_SWC1 $3 Software Control Register 1 SIM_SWC2 $4 Software Control Register 2 SIM_SWC3 $5 Software Control Register 3 SIM_MSHID $6 Most Significant Half JTAG ID SIM_LSHID $7 Least Significant Half JTAG ID SIM_PWR $8 Power Control Register Rese
Introduction Table 4-22 Flash Module Registers Address Map (Continued) (FM_BASE = $00 F400) Register Acronym Address Offset Register Description FM_USTAT $13 User Status Register FM_CMD $14 Command Register $15 Reserved $16 Reserved $17 Reserved $18 Data Buffer Register $19 Reserved FM_DATA FM_OPT1 $1A Reserved $1B Optional Data 1 Register Reserved FM_TSTSIG $1D Test Array Signature Register Part 5 Interrupt Controller (ITCN) 5.
restart the clocks and service the IRQ. An IRQ can only wake the core if the IRQ is enabled prior to entering wait or stop mode. 5.3.1 Normal Interrupt Handling Once the INTC has determined that an interrupt is to be serviced and which interrupt has the highest priority, an interrupt vector address is generated. Normal interrupt handling concatenates the Vector Base Address (VBA) and the vector number to determine the vector address, generating an offset into the vector table for each interrupt. 5.3.
Block Diagram 5.4 Block Diagram any0 Priority Level INT0 Level 0 46 -> 6 Priority Encoder 2 -> 4 Decode 6 INT VAB CONTROL IPIC any3 IACK Level 3 SR[9:8] Priority Level INT45 46 -> 6 Priority Encoder 6 PIC_EN 2 -> 4 Decode Figure 5-1 Interrupt Controller Block Diagram 5.5 Register Descriptions A register address is the sum of a base address and an address offset. The base address is defined at the system level and the address offset is defined at the module level.
Table 5-2 ITCN Register Summary (Continued) (ITCN_BASE = $00 F060) Register Acronym Base Address + Register Name Section Location IPR3 $3 Interrupt Priority Register 3 5.5.4 IPR4 $4 Interrupt Priority Register 4 5.5.5 VBA $5 Vector Base Address Register 5.5.6 FIM0 $6 Fast Interrupt Match 0 Register 5.5.7 FIVAL0 $7 Fast Interrupt 0 Vector Address Low Register 5.5.8 FIVAH0 $8 Fast Interrupt 0 Vector Address High Register 5.5.9 FIM1 $9 Fast Interrupt Match 1 Register 5.5.
Register Descriptions Add.
5.5.1.1 LVI IPL—Bits 15–14 This field is used to set the interrupt priority levels for a peripheral IRQ. This IRQ is limited to priorities 0 through 2 and is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.5.1.2 Reserved—Bits 13–10 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.5.1.
Register Descriptions 5.5.1.6 EOnCE Breakpoint Unit Interrupt Priority Level (BKPT_U IPL)— Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3 5.5.1.7 EOnCE Step Counter Interrupt Priority Level (STPCNT IPL)— Bits 1–0 This field is used to set the interrupt priority level for IRQs.
5.5.2.3 GPIOD Interrupt Priority Level (GPIOD IPL)—Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.5.2.4 Reserved—Bits 9–8 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.5.2.
Register Descriptions 5.5.2.8 PLL Loss of Reference or Change in Lock Status Interrupt Priority Level (PLL IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.5.
5.5.3.4 SCI Transmitter Idle Interrupt Priority Level (SCI_TIDL IPL)— Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.5.3.5 SCI Transmitter Empty Interrupt Priority Level (SCI_XMIT IPL)— Bits 7–6 This field is used to set the interrupt priority level for IRQs.
Register Descriptions 5.5.3.8 GPIOA Interrupt Priority Level (GPIOA IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.5.
5.5.4.4 Timer Channel 1 Interrupt Priority Level (TMR_1 IPL)—Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.5.4.5 Timer Channel 0 Interrupt Priority Level (TMR_0 IPL)—Bits 7–6 This field is used to set the interrupt priority level for IRQs.
Register Descriptions 5.5.5.2 PWM Fault Interrupt Priority Level (PWM_F IPL)— Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.5.5.3 Reload PWM Interrupt Priority Level (PWM_RL IPL)— Bits 5–4 This field is used to set the interrupt priority level for IRQs.
5.5.6 Vector Base Address Register (VBA) Base + $5 15 14 Read 0 0 0 0 13 12 11 10 9 7 6 5 4 3 2 1 0 0 0 0 0 0 VECTOR_BASE_ADDRESS Write RESET1 8 0 0 0 0 0 0 0 0 0 1. The 56F8014 resets to a value of 0x0000. This corresponds to reset addresses of 0x00 0000. Figure 5-8 Vector Base Address Register (VBA) 5.5.6.1 Reserved—Bits15—14 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.5.6.
Register Descriptions 5.5.8 Fast Interrupt 0 Vector Address Low Register (FIVAL0) Base + $7 15 14 13 12 11 Read 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 FAST INTERRUPT 0 VECTOR ADDRESS LOW Write RESET 0 0 0 0 0 0 0 0 0 0 0 Figure 5-10 Fast Interrupt 0 Vector Address Low Register (FIVAL0) 5.5.8.1 Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15—0 The lower 16 bits of the vector address used for Fast Interrupt 0.
Interrupt vector is set to any other priority. A Fast Interrupt automatically becomes the highest-priority level 2 interrupt regardless of its location in the interrupt table prior to being declared as Fast Interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to the vector table. 5.5.
Register Descriptions • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 5.5.13.2 Reserved—Bit 0 This bit is reserved or not implemented. It is read as 1 and cannot be modified by writing. 5.5.14 IRQ Pending Register 1 (IRQP1) Base + $D 15 14 13 12 11 10 9 Read 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 PENDING[32:17] Write RESET 1 1 1 1 1 1 1 1 1 Figure 5-16 IRQ Pending Register 1 (IRQP1) 5.5.14.
5.5.16.1 Interrupt (INT)—Bit 15 This read-only bit reflects the state of the interrupt to the 56800E core. • • 0 = No interrupt is being sent to the 56800E core 1 = An interrupt is being sent to the 56800E core 5.5.16.2 Interrupt Priority Level (IPIC)—Bits 14–13 These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E core. These bits indicate the priority level needed for a new IRQ to interrupt the current interrupt being sent to the 56800E core.
Resets 5.5.16.5 Reserved—Bits 4–2 This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing. 5.5.16.6 Reserved—Bits 1–0 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6 Resets 5.6.1 General Table 5-4 Reset Summary Reset Priority Core Reset 5.6.2 Source Characteristics RST Core reset from the SIM Description of Reset Operation 5.6.2.
• • SW Interrupt 0 SW Interrupt LP These interrupts are enabled at their fixed priority levels. Part 6 System Integration Module (SIM) 6.1 Introduction The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls distribution of resets and clocks and provides a number of control features.
Features • • • • • • • • • • Controls, with write protection, the enable/disable of Large Regulator Standby mode Controls to route functional signals to selected peripherals and I/O pads Controls deassertion sequence of internal resets Software-initiated reset Four 16-bit registers reset only by a Power-On Reset usable for general-purpose software control Timer channel Stop mode clocking controls SCI Stop mode clocking control to support LIN Sleep mode stop recovery Short addressing location control Regis
6.3 Register Descriptions Table 6-1 SIM Registers (SIM_BASE = $00 F140) Address Offset Address Acronym Register Name Section Location Base + $0 SIM_CTRL Control Register 6.3.1 Base + $1 SIM_RSTAT Reset Status Register 6.3.2 Base + $2 SIM_SWC0 Software Control Register 0 6.3.3 Base + $3 SIM_SWC1 Software Control Register 1 6.3.3 Base + $4 SIM_SWC2 Software Control Register 2 6.3.3 Base + $5 SIM_SWC3 Software Control Register 3 6.3.
Register Descriptions Add.
• 1 = Timer Channel 3 enabled in Stop mode 6.3.1.2 Timer Channel 2 Stop Disable (TC2_SD)—Bit 14 This bit enables the operation of the Timer Channel 2 peripheral clock in Stop mode. • • 0 = Timer Channel 2 disabled in Stop mode 1 = Timer Channel 2 enabled in Stop mode 6.3.1.3 Timer Channel 1 Stop Disable (TC1_SD)—Bit 13 This bit enables the operation of the Timer Channel 1 peripheral clock in Stop mode. • • 0 = Timer Channel 1 disabled in Stop mode 1 = Timer Channel 1 enabled in Stop mode 6.3.1.
Register Descriptions 6.3.1.
(COP) timer. It will not be set if an external or POR reset also occurred. If COPR is set as code starts executing, the COP reset vector in the vector table will be used. Otherwise, the normal reset vector is used. 6.3.2.4 External Reset (EXTR)—Bit 3 When set, this bit indicates that the previous system reset was caused by an external reset. It will only be set if the external reset pin was asserted or remained asserted after the Power-On Reset deasserted. 6.3.2.
Register Descriptions 6.3.5 Least Significant Half of JTAG ID (SIM_LSHID) This read-only register displays the least significant half of the JTAG ID for the chip. This register reads $401D. Base + $7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1 Write RESET Figure 6-6 Least Significant Half of JTAG ID (SIM_LSHID) 6.3.
The lower four bits of the GPIO A register can function as GPIO, PWM, or as additional clock output signals. GPIO has priority and is enabled/disabled via the GPIOA_PEREN. If GPIOA[3:0] are programmed to operate as peripheral outputs, then the choice between PWM and additional clock outputs is done here in the CLKOUT. The default state is for the peripheral function of GPIOA[3:0] to be programmed as PWM. This can be changed by altering PWM3 through PWM0.
Register Descriptions • • • 01101 = Reserved for factory test—Continuous peripheral clock 01110 = Reserved for factory test—Continuous inverted peripheral clock 01111 = Reserved for factory test—Continuous high-speed peripheral clock 6.3.8 SIM GPIO Peripheral Select Register (SIM_GPS) All of the peripheral pins on the 56F8014 share their Input/Output (I/O) with GPIO ports. To select peripheral or GPIO control, program the corresponding bit in the GPIOx_PEREN register in the GPIO module.
Note: This bit should only be changed while the Quad Timer module’s clock is disabled. See Section 6.3.9. Note: High-speed clocking is only available when the PLL is being used. Note: If the PWM sync signal is used as input to Timer 3 (See SIM_CTRL: TC3_INP, Section 6.3.1.7), then the clocks of the Quad Timer and PWM must be related, as shown in Table 6-2. 6.3.8.2 PWM Clock Rate (PCR)—Bit 14 This bit selects the clock speed for the PWM module.
Register Descriptions source clock to the chip. In this mode, make sure that no on-chip peripheral (including the GPIO) is driving this pin. 6.3.8.6 Configure GPIOB5 (CFG_B5)—Bit 9 This bit selects the alternate function for GPIOB5. • • 0 = T1 — Timer channel 1 input/output (default) 1 = FAULT3 — PWM FAULT3 input 6.3.8.7 Configure GPIOB4 (CFG_B4)—Bit 8 This bit selects the alternate function for GPIOB4. • • 0 = T0 — Timer channel 0 input/output (default) 1 = CLKO — Clock output 6.3.8.
• 11 = T3 — Timer Channel 3 input/output 6.3.8.13 Configure GPIOA4[1:0] (CFG_A4)—Bits 1–0 These bits select the alternate function for GPIOA4. • • • • 00 = PWM4 — PWM4 output 01 = PWM4 — PWM4 output 10 = FAULT1 — PWM FAULT1 input 11 = T2 — Timer Channel 2 input/output Note: When programming the CFG_* signals be careful so as not to connect two different I/O pins to the same peripheral input. For example, do not set CFG_B7 to select SCL and also set CFG_B0 to select SCL.
Register Descriptions • 1 = Clocks to the Quad Timer module are enabled 6.3.9.6 Reserved—Bit 5 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.3.9.7 • • SCI IPBus Clock Enable (SCI)—Bit 4 0 = The clock is not provided to the SCI module (the SCI module is disabled) 1 = Clocks to the SCI module are enabled 6.3.9.8 Reserved—Bit 3 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.3.9.
“Hard Coded” Address Portion Instruction Portion 6 Bits from I/O Short Address Mode Instruction 16 Bits from SIM_IOSALO Register 2 bits from SIM_IOSAHI Register Full 24-Bit for Short I/O Address Figure 6-12 I/O Short Address Determination With this register set, an interrupt driver can set the SIM_IOSALO register pair to point to its peripheral registers and then use the I/O Short addressing mode to reference them.
Clock Generation Overview Base + $E 15 14 13 12 11 10 9 Read 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 ISAL[21:6] Write RESET 1 1 1 1 1 1 1 1 1 Figure 6-14 I/O Short Address Location Low Register (SIM_IOSALO) 6.3.10.3 Input/Output Short Address Location (ISAL[21:6])—Bit 15–0 This field represents the lower 16 address bits of the “hard coded” I/O short address. 6.
Table 6-3 Clock Operation in Power-Down Modes (Continued) Mode Core Clocks Peripheral Clocks Peripheral clocks enabled Description Wait Core and memory clocks disabled Core executes WAIT instruction to enter this mode. Typically used for power-conscious applications. Possible recoveries from Wait mode to Run mode are: 1. Any interrupt 2. Executing a Debug mode entry command during the 56800E core JTAG interface 2.
Resets be put into its Standby mode (LRSTDBY) to reduce the power utilization of that regulator. All peripherals, except the COP/watchdog timer, run at the system clock (peripheral bus) frequency1, which is the same as the main processor frequency in this architecture. The COP timer runs at MSTR_OSC / 1024. The maximum frequency of operation is SYS_CLK = 32MHz.
EXTENDED_POR JTAG Power-On Reset (active low) POR pulse shaper Delay 64 MSTR_OSC Clocks External RESET IN RESET (active low) Memory Subsystem CLKGEN_RST OCCS COMBINED_RST PERIP_RST Delay 32 MSTR_OSC Clocks Peripherals pulse shaper COP (active low) Delay 32 sys clocks SW Reset pulse shaper Delay blocks assert immediately and deassert only after the programmed number of clock cycles.
Clocks 6.7 Clocks The memory, peripheral and core clocks all operate at the same frequency (32MHz max) with the exception of the TMR and PWM peripheral clocks, which have the option (using TCR and PCR) to operate three times faster. The SIM is responsible for stalling individual clocks as a response to various hold-off requests, low power modes, and other configuration parameters.
Maximum Delay = 64 MSTR_OSC cycles for POR reset extension and 32 MSTR_OSC cycles for combined reset extension RST MSTR_OSC Switch on falling OSC_CLK 96 MSTR_OSC cycles CKGEN_RST SYS_CLK_x2 SYS_CLK SYS_CLK_D SYS_CLK_DIV2 32 SYS_CLK cycles delay Switch on falling SYS_CLK PERIP_RST Switch on falling SYS_CLK 32 SYS_CLK cycles delay CORE_RST Figure 6-16 Timing Relationships of Reset Signal to Clocks 6.8 Interrupts The SIM generates no interrupts.
Flash Access Lock and Unlock Mechanisms memory chapter in MC56F8000RM, the 56F8000 Peripheral Reference Manual for details. When flash security mode is enabled, the 56F8014 will disable the core EOnCE debug capabilities. Normal program execution is otherwise unaffected. 7.2 Flash Access Lock and Unlock Mechanisms There are several methods that effectively lock or unlock the on-chip flash. 7.2.
in order to return to normal unsecured operation. Power-on reset will also reset both. The user is responsible for directing the device to invoke the flash programming subroutine to reprogram the word $0000 into program memory location $00 1FF7. This is done by, for example, toggling a specific pin, or by downloading a user-defined key through serial interfaces. Note: Flash contents can only be programmed for 1s to 0s. 7.
Configuration Table 8-2 GPIO External Signals Map Pins in shaded rows are not available in 56F8014 LQFP Package Pin GPIO Function Peripheral Function GPIOA0 PWM0 28 Defaults to A0 GPIOA1 PWM1 27 Defaults toA1 GPIOA2 PWM2 23 Defaults to A2 GPIOA3 PWM3 GPIOA4 PWM4 / FAULT1 / T2 22 SIM register SIM_GPS is used to select between PWM4, FAULT1, and T2 Defaults to A4 GPIOA5 PWM5 / FAULT2 / T3 20 SIM register SIM_GPS is used to select between PWM5, FAULT2, and T3 Defaults to A5 GPIOA6 FAU
Table 8-2 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8014 LQFP Package Pin GPIO Function Peripheral Function GPIOB6 RXD / SDA / CLKIN 32 SIM register SIM_GPS is used to select between RXD and SDA. CLKIN functionality is enabled using the PLL Control Register within the OCCS block.
Reset Values Add.
Add.
Reset Values Add.
Add.
56F8014 Information RS Reset Figure 8-4 GPIOD Register Map Summary Part 9 Joint Test Action Group (JTAG) 9.1 56F8014 Information Please contact your Freescale sales representative or authorized distributor for device/package-specific BSDL information. The TRST pin is not available in this package. The pin is tied to VDD in the package.
CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. Table 10-1 Absolute Maximum Ratings (VSS = 0V, VSSA = 0V) Characteristic Symbol Notes Min Max Unit Supply Voltage Range VDD -0.3 4.
General Characteristics 1. Pin Group 3 can tolerate 6V for less than 5 seconds when they are configured as ADC inputs or during reset. Pin Group 3 can tolerate 6V if they are configured as GPIO. 2. Continuous input current per pin is -2 mA Default Mode Pin Group 1: GPIO, TDI, TDO, TMS, TCK Pin Group 2: RESET, GPIOA7 Pin Group 3: ADC analog inputs 10.1.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 7. See Section 12.1 for more details on thermal design considerations. 56F8014 Technical Data, Rev.
General Characteristics Table 10-4 Recommended Operating Conditions (VREFL = 0V, VSSA = 0V, VSS = 0V ) Characteristic Symbol Notes Min Typ Max Unit Supply voltage VDD 3 3.3 3.6 V ADC Supply voltage VDDA 3 3.3 3.6 V ADC High Voltage Reference VREFH 3 — VDDA V Voltage difference VDD_IO to VDDA ΔVDD -0.1 0 0.1 V Voltage difference VSS_IO to VSSA ΔVSS -0.1 0 0.
10.2 DC Electrical Characteristics Table 10-5 DC Electrical Characteristics At Recommended Operating Conditions Symbol Notes Min Typ Max Unit Test Conditions Output Voltage High VOH Pin Group 1 2.4 — — V IOH = IOHmax Output Voltage Low VOL Pin Groups 1, 2 — — 0.4 V IOL = IOLmax Digital Input Current High pull-up enabled or disabled1 IIH Pin Groups 1, 2 — 0 +/- 2.5 μA VIN = 2.4V to 5.
DC Electrical Characteristics Table 10-6 Current Consumption per Power Supply Pin (Typical) Typical @ 3.3V, 25°C Mode Maximum@ 3.6V, 25°C Conditions IDD1 IDDA IDD1 IDDA RUN 32MHz Device Clock Relaxation Oscillator on PLL powered on Continuous MAC instructions with fetches from Program Flash All peripheral modules enabled. Quad Timer and PWM using 1x Clock ADC powered on and clocked 42mA 13.
Table 10-7 Power-On Reset Low-Voltage Parameters Characteristic Symbol Min Typ Max Unit Low-Voltage Interrupt for 3.3V supply1 VEI3.3 2.60 2.7 — V Low-Voltage Interrupt for 2.5V supply2 VE12.5 2.05 2.15 — V Low-Voltage Interrupt Recovery Hysteresis VEIH — 50 — mV Power-On Reset3 POR — 1.8 1.9 V 1. When VDD drops below VEI3.3, an interrupt is generated. 2. When VDD drops below VEI32.5, an interrupt is generated. 3. Power-On Reset occurs whenever the internally regulated 2.
Flash Memory Characteristics Low VIH Input Signal High 90% 50% 10% Midpoint1 VIL Fall Time Rise Time Note: The midpoint is VIL + (VIH – VIL)/2.
10.5 External Clock Operation Timing Table 10-10 External Clock Operation Timing Requirements1 Characteristic Symbol Min Typ Max Unit Frequency of operation (external clock driver)2 fosc 4 8 8 MHz Clock Pulse Width3 tPW 6.25 — — ns External Clock Input Rise Time4 trise — — 3 ns External Clock Input Fall Time5 tfall — — 3 ns 1. 2. 3. 4. 5. Parameters listed are guaranteed by design. See Figure 10-4 for details on using the recommended connection of an external clock driver.
Relaxation Oscillator Timing 10.7 Relaxation Oscillator Timing Table 10-12 Relaxation Oscillator Timing Characteristic Symbol Minimum Typical Maximum Relaxation Oscillator output frequency Normal Mode1 Standby Mode fop — Relaxation Oscillator stabilization time2 troscs — 1 tjitterrosc — 400 ps Minimum tuning step size .08 % Maximum tuning step size 40 % — 8.05 200 Cycle-to-cycle jitter.
10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing Note: All the address and data buses described here are internal.
Serial Peripheral Interface (SPI) Timing 10.9 Serial Peripheral Interface (SPI) Timing Table 10-14 SPI Timing1 Characteristic Symbol Cycle time Master Slave Min Max Unit 125 62.5 — — ns ns — 31 — — ns ns — 125 — — ns ns 50 31 — — ns ns 50 31 — — ns ns 20 0 — — ns ns 0 2 — — ns ns 4.8 15 ns 3.7 15.2 ns — — 4.5 20.4 ns ns 0 0 — — ns ns — — 11.5 10.0 ns ns — — 9.7 9.
1. Parameters listed are guaranteed by design. 1 SS SS is held High on master (Input) tC tR tF tCL SCLK (CPOL = 0) (Output) tCH tF tR tCL SCLK (CPOL = 1) (Output) tDH tCH tDS MISO (Input) MSB in Bits 14–1 tDI MOSI (Output) Master MSB out tDV Bits 14–1 tF LSB in tDI(ref) Master LSB out tR Figure 10-7 SPI Master Timing (CPHA = 0) 56F8014 Technical Data, Rev.
Serial Peripheral Interface (SPI) Timing SS (Input) SS is held High on master tC tF tR tCL SCLK (CPOL = 0) (Output) tCH tF tCL SCLK (CPOL = 1) (Output) tCH tDS tR MISO (Input) MSB in tDH Bits 14–1 tDI tDV(ref) MOSI (Output) LSB in tDV Master MSB out tDI(ref) Bits 14– 1 Master LSB out tF tR Figure 10-8 SPI Master Timing (CPHA = 1) SS (Input) tC tF tCL SCLK (CPOL = 0) (Input) tCH tELD tCL SCLK (CPOL = 1) (Input) tCH tA MISO (Output) Slave MSB out tDV tDH MSB in tF tR B
SS (Input) tF tC tR tCL SCLK (CPOL = 0) (Input) tCH tELG tELD tCL SCLK (CPOL = 1) (Input) tDV tCH tR tA MISO (Output) tD tF Slave MSB out Bits 14–1 tDS tDV tDI tDH MOSI (Input) MSB in Slave LSB out Bits 14–1 LSB in Figure 10-10 SPI Slave Timing (CPHA = 1) 10.
Quad Timer Timing Timer Inputs PIN PINHL PINHL POUT POUTHL POUTHL Timer Outputs Figure 10-11 Timer Timing 56F8014 Technical Data, Rev.
10.11 Serial Communication Interface (SCI) Timing Table 10-16 SCI Timing1 Characteristic Symbol Min Max Unit See Figure BR — (fMAX/16) Mbps — RXD3 Pulse Width RXDPW 0.965/BR 1.04/BR ns 10-12 TXD4 Pulse Width TXDPW 0.965/BR 1.
Inter-Integrated Circuit Interface (I2C) Timing 10.12 Inter-Integrated Circuit Interface (I2C) Timing Table 10-17 I2C Timing Standard Mode Characteristic Fast Mode Symbol Unit Minimum Maximum Minimum Maximum fSCL 0 100 0 400 tHD; STA 4.0 0.6 μs LOW period of the SCL clock tLOW 4.7 1.25 μs HIGH period of the SCL clock tHIGH 4.0 0.6 μs Set-up time for a repeated START condition tSU; STA 4.7 0.
SDA tSU; DAT tLOW tHD; STA tBUF tSP SCL S tSU; STA tHD; STA tHD; DAT tHIGH tSU; STO BR P S Figure 10-14 Timing Definition for Fast and Standard Mode Devices on the I2C Bus 10.
JTAG Timing TCK (Input) tDS TDI TMS (Input) tDH Input Data Valid tDV TDO (Output) Output Data Valid tTS TDO (Output) Figure 10-16 Test Access Port Timing Diagram 56F8014 Technical Data, Rev.
10.14 Analog-to-Digital Converter (ADC) Parameters Table 10-19 ADC Parameters1 Parameter Symbol Min Typ Max Unit Resolution RES 12 — 12 Bits ADC internal clock fADIC 0.1 — 5.
Equivalent Circuit for ADC Inputs 5. LSB = Least Significant Bit = 0.806mV 6. Pin groups are detailed following Table 10-1. 7. The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the ADC. 10.15 Equivalent Circuit for ADC Inputs Figure 10-17 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time that S3 is closed/open.
C1 2 X C1 : Singled Ended Mode : Differential Mode Equivalent Circuit for A/D Loading S1 ADC Input 125 Ohm ESD Resistor channel mux equiv resistance 100 Ohms S1 C1 S/H S1 1 2 3 (VREFHx - VREFLx) / 2 C1 S1 1. 2. 3. 4. 5. Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8 pF Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pF 8 pF noise damping capacitor C1 = 1.
Power Consumption +C: internal [dynamic component] +D: external [dynamic component] +E: external [static] A, the internal [static component], is comprised of the DC bias currents for the oscillator, leakage currents, PLL, and voltage references. These sources operate independently of processor state or operating frequency. B, the internal [state-dependent component], reflects the supply current required by certain on-chip resources only when those resources are in use.
In previous discussions, power consumption due to parasitics associated with pure input pins is ignored, as it is assumed to be negligible. 56F8014 Technical Data, Rev.
56F8014 Package and Pin-Out Information Part 11 Packaging 11.1 56F8014 Package and Pin-Out Information VDD_IO VSS_IO GPIOA1/PWM1 GPIOA0/PWM0 TDI/GPIOD0 TMS/GPIOD3 TDO/GPIOD1 GPIOB6/RXD/SDA/CLKIN This section contains package and pin-out information for the 56F8014. This device comes in a 32-pin Low-profile Quad Flat Pack (LQFP).
Table 11-1 56F8014 32-Pin LQFP Package Identification by Pin Number1 Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
A –T–, –U–, –Z– 56F8014 Package and Pin-Out Information 4X A1 32 0.20 (0.008) AB T–U Z 25 1 –U– –T– B V AE P B1 DETAIL Y 17 8 V1 AE DETAIL Y 9 4X –Z– 9 0.20 (0.008) AC T–U Z S1 S DETAIL AD G –AB– 0.10 (0.004) AC AC T–U Z –AC– BASE METAL ÉÉ ÉÉ ÉÉ ÉÉ F 8X M R J M N D 0.20 (0.008) SEATING PLANE SECTION AE–AE K X DETAIL AD Q GAUGE PLANE W H 0.250 (0.010) C E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3.
Part 12 Design Considerations 12.1 Thermal Design Considerations An estimation of the chip junction temperature, TJ, can be obtained from the equation: TJ = TA + (RθJΑ x PD) where : TA = Ambient temperature for the package (oC) RθJΑ = Junction-to-ambient thermal resistance (oC/W) PD = Power dissipation in the package (W) The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal performance.
Electrical Design Considerations ΨJT PD = Thermal characterization parameter (oC/W) = Power dissipation in package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction.
• • PCB trace lengths should be minimal for high-frequency signals Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and VSS circuits. • Take special care to minimize noise levels on the VREF, VDDA and VSSA pins • Using separate power planes for VDD and VDDA and separate ground planes for VSS and VSSA is recommended.
Electrical Design Considerations Part 13 Ordering Information Table 13-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor sales office or authorized distributor to determine availability and to order parts. Table 13-1 56F8014 Ordering Information Part Supply Voltage Package Type Pin Count Frequency (MHz) Abient Temperature Range Order Number MC56F8014 3.0–3.6 V Low-Profile Quad Flat Pack (LQFP) 32 32 -40° to + 105° C MC56F8014VFAE* MC56F8014 3.0–3.
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