Datasheet

56F8014 Technical Data, Rev. 11
12 Freescale Semiconductor
Figure 1-3 56F8014 Peripheral I/O Pin-Out
To/From IPBus Bridge
3
to PWM
Sync0,
Sync1
Over/Under
Limits
ADC
ANA0, 1, 3
ANA2
V
REFH
, V
REFL
ANB2
ANB0, 1, 3
IPBus
3
2
V
REFH
, V
REFL
ANA2
ANB2
ANA0, 1, 3
3
SPI
I
2
C
SCI
2
T2o, T3o
T3i T2/3
T1
T0
Timer
PWM
PWM0 - 3
Fault3
Fault0
Fault1, 2
PWM4, 5
PWM4, 5
PWM0 - 3
Fault1, 2
Fault0
Fault3
T2, 3
2
3
from ADC
I
2
C is muxed with both SPI and SCI.
T2 and T3 are muxed with SPI and PWM.
T1
T0
CLKO
TXD, RXD
2
2
2
2
T2, 3
ANB0, 1, 3
GPIOA0 - 3
GPIOA4 - 5
GPIOA6
GPIOB5
GPIOB4
GPIOB6 - 7
GPIOB0 - 1
GPIOB2 - 3
GPIOC0, 1, 3
GPIOC2, 6
GPIOC4, 5, 7
SDA, SCL
SCLK, SS
MISO, MOSI
4
2
2
Output Controls
2
2
2
(Continued from Figure 1-2)
Reload
Pulse