Datasheet

56F8014 Technical Data, Rev. 11

28 Freescale Semiconductor

3.4 Block Diagram

Figure 3-2 provides a block diagram which shows how the 56F8014 creates its internal clock, using the

relaxation oscillator as an 8MHz clock reference for the PLL.

Figure 3-2 OCCS Block Diagram with Relaxation Oscillator

TRIM[9:0]

ROSB

ROPD

Relaxation

OSC

Bus Interface and

Control

Bus

Interface

GPIOB6 / RXD

PRECS

MUX

MSTR_OSC

SYS_CLK_x2

source to the SIM

(64MHz max)

ZSRC

HS PERF CLK

(96MHz max)

Postscaler

(÷ 1, 2, 4, 8, 16, 32)

Postscaler

(÷ 1, 2, 4, 8, 16, 32)

÷ 3

÷ 2

PLL

X 24

Lock

Detector

Loss of

Reference

Clock

Detector

Loss of Reference Clock Interrupt

LCK

OUT

FEEDBACK

PLLCOD

FOUT