Datasheet

56F8014 Technical Data, Rev. 11
34 Freescale Semiconductor
The following tables list all of the peripheral registers required to control or access the peripherals.
Table 4-6 Data Memory Peripheral Base Address Map Summary
Peripheral Prefix Base Address Table Number
Timer TMRn X:$00 F000 4-7
PWM PWM X:$00 F040 4-8
ITCN ITCN X:$00 F060 4-9
ADC ADC X:$00 F080 4-10
SCI SCI X:$00 F0B0 4-11
SPI SPI X:$00 F0C0 4-12
I
2
C
I2C X:$00 F0D0 4-13
COP COP X:$00 F0E0 4-14
CLK, PLL, OSC, TEST OCCS X:$00 F0F0 4-15
GPIO Port A GPIOA X:$00 F100 4-16
GPIO Port B GPIOB X:$00 F110 4-17
GPIO Port C GPIOC X:$00 F120 4-18
GPIO Port D GPIOD X:$00 F130 4-19
SIM SIM X:$00 F140 4-20
Power Supervisor PS X:$00 F160 4-21
FM FM X:$00 F400 4-22
Table 4-7 Quad Timer Registers Address Map
(TMR_BASE = $00 F000)
Register Acronym Address Offset Register Description
TMR0_COMP1 $0 Compare Register 1
TMR0_COMP2 $1 Compare Register 2
TMR0_CAPT $2 Capture Register
TMR0_LOAD $3 Load Register
TMR0_HOLD $4 Hold Register
TMR0_CNTR $5 Counter Register
TMR0_CTRL $6 Control Register
TMR0_SCTRL $7 Status and Control Register
TMR0_CMPLD1 $8 Comparator Load Register 1
TMR0_CMPLD2 $9 Comparator Load Register 2
TMR0_CSCTRL $A Comparator Status and Control Register
Reserved
TMR1_COMP1 $10 Compare Register 1
TMR1_COMP2 $11 Compare Register 2