Datasheet

Peripheral Memory Mapped Registers

56F8014 Technical Data, Rev. 11

Freescale Semiconductor 35

TMR1_CAPT $12 Capture Register

TMR1_LOAD $13 Load Register

TMR1_HOLD $14 Hold Register

TMR1_CNTR $15 Counter Register

TMR1_CTRL $16 Control Register

TMR1_SCTRL $17 Status and Control Register

TMR1_CMPLD1 $18 Comparator Load Register 1

TMR1_CMPLD2 $19 Comparator Load Register 2

TMR1_CSCTRL $1A Comparator Status and Control Register

Reserved

TMR2_COMP1 $20 Compare Register 1

TMR2_COMP2 $21 Compare Register 2

TMR2_CAPT $22 Capture Register

TMR2_LOAD $23 Load Register

TMR2_HOLD $24 Hold Register

TMR2_CNTR $25 Counter Register

TMR2_CTRL $26 Control Register

TMR2_SCTRL $27 Status and Control Register

TMR2_CMPLD1 $28 Comparator Load Register 1

TMR2_CMPLD2 $29 Comparator Load Register 2

TMR2_CSCTRL $2A Comparator Status and Control Register

Reserved

TMR3_COMP1 $30 Compare Register 1

TMR3_COMP2 $31 Compare Register 2

TMR3_CAPT $32 Capture Register

TMR3_LOAD $33 Load Register

TMR3_HOLD $34 Hold Register

TMR3_CNTR $35 Counter Register

TMR3_CTRL $36 Control Register

TMR3_SCTRL $37 Status and Control Register

TMR3_CMPLD1 $38 Comparator Load Register 1

TMR3_CMPLD2 $39 Comparator Load Register 2

TMR3_CSCTRL $3A Comparator Status and Control Register

Table 4-7 Quad Timer Registers Address Map (Continued)

(TMR_BASE = $00 F000)