Datasheet

Peripheral Memory Mapped Registers

56F8014 Technical Data, Rev. 11

Freescale Semiconductor 37

ITCN_FIM1 $9 Fast Interrupt Match 1 Register

ITCN_FIVAL1 $A Fast Interrupt Vector Address Low 1 Register

ITCN_FIVAH1 $B Fast Interrupt Vector Address High 1 Register

ITCN_IRQP 0 $C IRQ Pending Register 0

ITCN_IRQP 1 $D IRQ Pending Register 1

ITCN_IRQP 2 $E IRQ Pending Register 2

Reserved

ITCN_ICTRL $12 Interrupt Control Register

Reserved

Table 4-10 Analog-to-Digital Converter Registers Address Map

(ADC_BASE = $00 F080)

ADC_CTRL1 $0 Control Register 1

ADC_CTRL2 $1 Control Register 2

ADC_ZXCTRL $2 Zero Crossing Control Register

ADC_CLIST 1 $3 Channel List Register 1

ADC_CLIST 2 $4 Channel List Register 2

ADC_SDIS $5 Sample Disable Register

ADC_STAT $6 Status Register

ADC_LIMSTAT $7 Limit Status Register

ADC_ZXSTAT $8 Zero Crossing Status Register

ADC_RSLT0 $9 Result Register 0

ADC_RSLT1 $A Result Register 1

ADC_RSLT2 $B Result Register 2

ADC_RSLT3 $C Result Register 3

ADC_RSLT4 $D Result Register 4

ADC_RSLT5 $E Result Register 5

ADC_RSLT6 $F Result Register 6

ADC_RSLT7 $10 Result Register 7

ADC_LOLIM0 $11 Low Limit Register 0

ADC_LOLIM1 $12 Low Limit Register 1

ADC_LOLIM2 $13 Low Limit Register 2

ADC_LOLIM3 $14 Low Limit Register 3

ADC_LOLIM4 $15 Low Limit Register 4

ADC_LOLIM5 $16 Low Limit Register 5

Table 4-9 Interrupt Control Registers Address Map (Continued)

(ITCN_BASE = $00 F060)