Datasheet

56F8014 Technical Data, Rev. 11
4 Freescale Semiconductor
56F8014 Block Diagram
Program Controller
and Hardware
Looping Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Address
Generation Unit
Bit
Manipulation
Unit
16-Bit
56800E Core
Interrupt
Controller
4
Unified Data /
Program RAM
4KB
PDB
PDB
XAB1
XAB2
XDB2
CDBR
SPI or I
2
C
or Timer
or GPIOB
IPBus Bridge (IPBB)
System Bus
Control
R/W Control
Memory
PAB
PAB
CDBW
CDBR
CDBW
JTAG/EOnCE
Port or
GPIOD
Digital Reg
Analog Reg
Low-Voltage
Supervisor
V
CAP
V
DD
V
SS_IO
V
DDA
V
SSA
4
RESET
5
Timer or
GPIOB
AD0
2
4
Clock
Generator*
System
Integration
Module
P
O
R
O
S
C
PWM Outputs
PWM
or Timer Port
or GPIOA
*Includes On-Chip
Relaxation Oscillator
COP/
Watchdog
AD1
4
Program Memory
8K x 16 Flash
ADC
or
GPIOC
SCI
or I
2
C
or GPIOB
2
2
• Up to 32 MIPS at 32MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 16KB Program Flash
• 4KB Unified Data/Program RAM
• One 5-channel PWM module
• Two 4-channel 12-bit ADCs
• One Serial Communication Interface (SCI) with LIN
slave functionality
• One Serial Peripheral Interface (SPI)
• One 16-bit Quad Timer
• One Inter-Integrated Circuit (I
2
C) Port
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• Integrated Power-On Reset and Low-Voltage Interrupt
Module
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 26 GPIO lines
• 32-pin LQFP Package
56F8014 General Description