Datasheet
Peripheral Memory Mapped Registers
56F8014 Technical Data, Rev. 11
Freescale Semiconductor 41
Table 4-18 GPIOC Registers Address Map
(GPIOC_BASE = $00 F120)
Register Acronym Address Offset Register Description
GPIOC_PUPEN $0 Pull-up Enable Register
GPIOC_DATA $1 Data Register
GPIOC_DDIR $2 Data Direction Register
GPIOC_PEREN $3 Peripheral Enable Register
GPIOC_IASSRT $4 Interrupt Assert Register
GPIOC_IEN $5 Interrupt Enable Register
GPIOC_IEPOL $6 Interrupt Edge Polarity Register
GPIOC_IPEND $7 Interrupt Pending Register
GPIOC_IEDGE $8 Interrupt Edge-Sensitive Register
GPIOC_PPOUTM $9 Push-Pull Output Mode Control Register
GPIOC_RDATA $A Raw Data Register
GPIOC_DRIVE $B Drive Strength Control Register
Table 4-19 GPIOD Registers Address Map
(GPIOD_BASE = $00 F130)
Register Acronym Address Offset Register Description
GPIOD_PUPEN $0 Pull-up Enable Register
GPIOD_DATA $1 Data Register
GPIOD_DDIR $2 Data Direction Register
GPIOD_PEREN $3 Peripheral Enable Register
GPIOD_IASSRT $4 Interrupt Assert Register
GPIOD_IEN $5 Interrupt Enable Register
GPIOD_IEPOL $6 Interrupt Edge Polarity Register
GPIOD_IPEND $7 Interrupt Pending Register
GPIOD_IEDGE $8 Interrupt Edge-Sensitive Register
GPIOD_PPOUTM $9 Push-Pull Output Mode Control Register
GPIOD_RDATA $A Raw Data Register
GPIOD_DRIVE $B Drive Strength Control Register
