Datasheet

Block Diagram
56F8014 Technical Data, Rev. 11
Freescale Semiconductor 45
5.4 Block Diagram
Figure 5-1 Interrupt Controller Block Diagram
5.5 Register Descriptions
A register address is the sum of a base address and an address offset. The base address is defined at the
system level and the address offset is defined at the module level. The ITCN module has 16 registers.
Table 5-2 ITCN Register Summary
(ITCN_BASE = $00 F060)
Register
Acronym
Base Address + Register Name Section Location
IPR0 $0 Interrupt Priority Register 0 5.5.1
IPR1 $1 Interrupt Priority Register 1 5.5.2
IPR2 $2 Interrupt Priority Register 2 5.5.3
Priority
Level
2 -> 4
Decode
INT0
Priority
Level
2 -> 4
Decode
INT45
Level 0
46 -> 6
Priority
Encoder
any0
Level 3
46 -> 6
Priority
Encoder
any3
INT
VAB
IPIC
CONTROL
6
6
PIC_EN
IACK
SR[9:8]