Datasheet

Register Descriptions
56F8014 Technical Data, Rev. 11
Freescale Semiconductor 57
5.5.8 Fast Interrupt 0 Vector Address Low Register (FIVAL0)
Figure 5-10 Fast Interrupt 0 Vector Address Low Register (FIVAL0)
5.5.8.1 Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15—0
The lower 16 bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAH0
to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.
5.5.9 Fast Interrupt 0 Vector Address High Register (FIVAH0)
Figure 5-11 Fast Interrupt 0 Vector Address High Register (FIVAH0)
5.5.9.1 Reserved—Bits 15–5
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.5.9.2 Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0
The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAL0
to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.
5.5.10 Fast Interrupt 1 Match Register (FIM1)
Figure 5-12 Fast Interrupt 1 Match Register (FIM1)
5.5.10.1 Reserved—Bits 15–6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.5.10.2 Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)—Bits 5–0
These values determine which IRQ will be Fast Interrupt 1. Fast Interrupts vector directly to a service
routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table
first. IRQs used as Fast Interrupts must be set to priority level 2. Unexpected results will occur if a Fast
Base + $7
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
FAST INTERRUPT 0 VECTOR ADDRESS LOW
Write
RESET
0000000000000000
Base + $8
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
0 0 0 0 0 0 0 0 0 0 0
FAST INTERRUPT 0 VECTOR
ADDRESS HIGH
Write
RESET
0000000000000000
Base + $9
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
0 0 0 0 0 0 0 0 0 0
FAST INTERRUPT 1
Write
RESET
0000000000000000