Datasheet

56F8014 Technical Data, Rev. 11
62 Freescale Semiconductor
• SW Interrupt 0
• SW Interrupt LP
These interrupts are enabled at their fixed priority levels.
Part 6 System Integration Module (SIM)
6.1 Introduction
The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls
distribution of resets and clocks and provides a number of control features. The System Integration Module
is responsible for the following functions:
• Reset sequencing
• Clock control & distribution
• Stop/Wait control
• System status registers
• Registers for software access to the JTAG ID of the chip
• Test registers
• Power control
• I/O pad multiplexing
These are discussed in more detail in the sections that follow.
6.2 Features
The SIM has the following features:
• Reset sequencing
— Core and Peripheral Clock control & distribution
— Stop/Wait mode control
— System status
— Power control
— Control I/O multiplexing
• System bus clocks with pipeline hold-off support
• System clocks for non-pipelined interfaces
• Peripheral clocks for Quad Timer and PWM with high-speed (3X) option
• Power-saving clock gating for peripherals
• Three power modes (Run, Wait, Stop) to control power utilization
— Stop mode shuts down the 56800E core, system clock, and peripheral clock
— Wait mode shuts down the 56800E core and unnecessary system clock operation
— Run mode supports full part operation
• Controls, with write protection, the enable/disable of 56800E core WAIT and STOP instructions