Datasheet

56F8014 Technical Data, Rev. 11
74 Freescale Semiconductor
• 11 = T3 — Timer Channel 3 input/output
6.3.8.13 Configure GPIOA4[1:0] (CFG_A4)—Bits 1–0
These bits select the alternate function for GPIOA4.
• 00 = PWM4 — PWM4 output
• 01 = PWM4 — PWM4 output
• 10 = FAULT1 — PWM FAULT1 input
• 11 = T2 — Timer Channel 2 input/output
Note: When programming the CFG_* signals be careful so as not to connect two different I/O pins to the
same peripheral input. For example, do not set CFG_B7 to select SCL and also set CFG_B0 to select
SCL. If this occurs for an output signal, then the signal will be routed to two I/O pins. For input
signals, the values on the two I/O pins will be ORed together before reaching the peripheral.
6.3.9 Peripheral Clock Enable Register (SIM_PCE)
The Peripheral Clock Enable register is used to enable or disable clocks to the peripherals as a power
savings feature. The clocks can be individually controlled for each peripheral on the chip. The
corresponding peripheral should itself be disabled while its clock is shut off.
Figure 6-11 Peripheral Clock Enable Register (SIM_PCE)
6.3.9.1 I
2
C Clock Enable (I2C)—Bit 15
• 0 = The clock is not provided to the I
2
C module (the I
2
C module is disabled)
• 1 = Clocks to the I
2
C module are enabled
6.3.9.2 Reserved—Bit 14
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.3.9.3 Analog-to-Digital Converter IPBus Clock Enable (ADC)—Bit 13
• 0 = The clock is not provided to the ADC module (the ADC module is disabled)
• 1 = Clocks to the ADC module are enabled
6.3.9.4 Reserved—Bits 12–7
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.3.9.5 Timer Clock Enable (TMR)—Bit 6
• 0 = The clock is not provided to the Quad Timer module (the Quad Timer module is disabled)
Base + $C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
I2C
0
ADC
0 0 0 0 0 0
TMR
0
SCI
0
SPI
0
PWM
Write
RESET
0000000 0 00000 00 0