Datasheet

56F8014 Technical Data, Rev. 11
8 Freescale Semiconductor
— External clock source
• On-chip regulators for digital and analog circuitry to lower cost and reduce noise
• JTAG/EOnCE debug programming interface for real-time debugging
1.1.4 Energy Information
• Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
• On-chip regulators for digital and analog circuitry to lower cost and reduce noise
• Wait and Stop modes available
• ADC smart power management
• Each peripheral can be individually disabled to save power
1.2 56F8014 Description
The 56F8014 is a member of the 56800E core-based family of Digital Signal Controllers (DSCs). It
combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with
a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,
configuration flexibility, and compact program code, the 56F8014 is well-suited for many applications.
The 56F8014 includes many peripherals that are especially useful for industrial control, motion control,
home appliances, general purpose inverters, smart sensors, fire and security systems, switched-mode
power supplies, power management, and medical monitoring applications.
The 56800E core is based on a dual Harvard-style architecture consisting of three execution units
operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style
programming model and optimized instruction set allow straightforward generation of efficient, compact
DSP and control code. The instruction set is also highly efficient for C compilers to enable rapid
development of optimized control applications.
The 56F8014 supports program execution from internal memories. Two data operands can be accessed
from the on-chip data RAM per instruction cycle. The 56F8014 also offers up to 26 General Purpose
Input/Output (GPIO) lines, depending on peripheral configuration.
The 56F8014 Digital Signal Controller includes 16KB of Program Flash and 4KB of Unified
Data/Program RAM. Program Flash memory can be independently bulk erased or erased in pages.
Program Flash page erase size is 512 Bytes/256 Words.
A full set of programmable peripherals—PWM, ADCs, SCI, SPI, I
2
C, Quad Timer—support various
applications. Each peripheral can be independently shut down to save power. Any pin in these peripherals
can also be used as a General Purpose Input/Outputs (GPIO).
1.3 Award-Winning Development Environment
Processor Expert
TM
(PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs), demonstration board kit and
development system cards will support concurrent engineering. Together, PE, CodeWarrior and EVMs