56F8036 Data Sheet Technical Data 56F8000 16-bit Digital Signal Controllers MC56F8036 Rev. 6 02/2010 freescale.
Document Revision History Version History Description of Change Rev. 0 Initial public release. Rev. 1 • In Table 10-4, added an entry for flash data retention with less than 100 program/erase cycles (minimum 20 years). • In Table 10-6, changed the device clock speed in STOP mode from 8MHz to 4MHz. • In Table 10-12, changed the typical relaxation oscillator output frequency in Standby mode from 400kHz to 200kHz.
56F8036 General Description • Up to 32 MIPS at 32MHz core frequency • One Queued Serial Peripheral Interface (QSPI) • DSP and MCU functionality in a unified, C-efficient architecture • Freescale’s scalable controller area network (MSCAN) 2.
56F8036 Data Sheet Table of Contents Part 1 Overview. . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 1.2 1.3 1.4 1.5 1.6 56F8036 Features. . . . . . . . . . . . . . . . . . . 5 56F8036 Description. . . . . . . . . . . . . . . . . 7 Award-Winning Development Environment . . . . . . . . . . . . . . . . . . . 8 Architecture Block Diagram . . . . . . . . . . . 8 Product Documentation . . . . . . . . . . . . . 16 Data Sheet Conventions . . . . . . . . . . . . . 16 Part 2 Signal/Connection Descriptions . .
6F8036 Features Part 1 Overview 1.1 56F8036 Features 1.1.1 • • • • • • • • • • • • • • 1.1.
– External GPIO – Internal timers – Analog comparator outputs – ADC conversion result which compares with values of ADC high- and low-limit registers to set PWM output • Two independent 12-bit Analog-to-Digital Converters (ADCs) — 2 x 5 channel inputs — Supports both simultaneous and sequential conversions — ADC conversions can be synchronized by both PWM and timer modules — Sampling rate up to 2.
56F8036 Description — Fully compliant with CAN protocol - Version 2.
development of optimized control applications. The 56F8036 supports program execution from internal memories. Two data operands can be accessed from the on-chip data RAM per instruction cycle. The 56F8036 also offers up to 39 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. The 56F8036 Digital Signal Controller includes 64KB of Program Flash and 8KB of Unified Data/Program RAM. Program Flash memory can be independently bulk erased or erased in pages.
Architecture Block Diagram DSP56800E Core Program Control Unit PC LA LA2 HWS0 HWS1 FIRA OMR SR LC LC2 FISR Address Generation Unit (AGU) Instruction Decoder Interrupt Unit ALU1 ALU2 R0 R1 R2 R3 R4 R5 N M01 N3 Looping Unit Program Memory SP XAB1 XAB2 PAB PDB Data / Program RAM CDBW CDBR XDB2 A2 B2 C2 D2 BitManipulation Unit Enhanced OnCE™ JTAG TAP Y A1 B1 C1 D1 Y1 Y0 X0 MAC and ALU A0 B0 C0 D0 IPBUS Interface Data Arithmetic Logic Unit (ALU) Multi-Bit Shifter Figure 1-1 56800E Core Blo
To/From IPBus Bridge OCCS (ROSC / PLL / OSC) Interrupt Controller Low-Voltage Interrupt GPIO A POR & LVI GPIO B System POR GPIO C SIM GPIO D RESET (Muxed with GPIOA7) COP Reset COP IPBus (Continues on Figure 1-3) Figure 1-2 Peripheral Subsystem 56F8036 Data Sheet, Rev.
Architecture Block Diagram To/From IPBus Bridge IPBus INTC SYNC PIT0 MSTR_CNT_EN 3 MSTR_CNT_EN DAC SYNC on Figure 1-5 SYNC PIT1 MSTR_CNT_EN SYNC PIT2 2 3 Sync0, Sync1 Over/Under Limits SYNC0, SYNC1 on Figure 1-7 LIMIT on Figure 1-6 ANA0 ANA0 on Figure 1-5 GPIOC2 ANA2 (VREFHA) GPIOC3 ANA3 (VREFLA) GPIOC8 ANA4 GPIOC1 ANA1 ADC ANB0 ANB0 on Figure 1-5 ANB2 (VREFHA) ANB3 (VREFLB) ANB4 ANB1 GPIOC6 GPIOC7 GPIOC12 GPIOC5 Figure 1-3 56F8036 I/O Pin-Out Muxing (Part 1/5) 56F8036 Data Sheet,
To/From IPBus Bridge QSCI0 RXD0, TXD0 2 GPIOB6 - 7 TA2, TA3 on Figure 1-7 GPIOB2 - 3 MISO0, MOSI0 QSPI0 SCLK0, SS0 2 2 2 I2C SCL, SDA GPIOB0 - 1 2 2 2 GPIOB8 - 9 MSCAN CANTX, CANRX 2 IPBus Figure 1-4 56F8036 I/O Pin-Out Muxing (Part 2/5) 56F8036 Data Sheet, Rev.
Architecture Block Diagram To/From IPBus Bridge FAULT1 on Figure 1-6 TA2 on Figure 1-7 CMP_IN1 CMP_IN3 GPIOA8 CMPAI1 GPIOC0 CMPAI3 CMPA CMP_OUT CMP_IN2 Export Import CMPAO on Figure 1-6, Figure 1-7 GPIOA10 CMPAI2 ANA0 on Figure 1-3 GPIOB10 DAC0 2 3 TA0o, TA1o on Figure 1-7 DAC SYNC on Figure 1-3 RELOAD on Figure 1-6 DAC1 GPIOB11 ANB0 on Figure 1-3 Import Export CMP_IN2 CMP_OUT GPIOA11 CMPBI2 CMPBO on Figure 1-6, Figure 1-7 CMPB CMP_IN3 CMP_IN1 GPIOC4 CMPBI3 CMPBI1 TA3 on Figure 1-7 GPIOA9
To/From IPBus Bridge TA0 on Figure 1-7 GPIOA6 2 TA2 - 3 on Figure 1-7 GPIOA0 - 3 4 PWM0 - 3 FAULT0 GPIOA4 - 5 2 PWMA4 - 5 1 2 PWM FAULT1 FAULT1 on Figure 1-5 FAULT2 RELOAD PSRC0 - 1 1 FAULT3 FAULT2 on Figure 1-5 TA1 on Figure 1-7 GPIOB5 RELOAD on Figure 1-7, Figure 1-5 IPBus CMPAO on Figure 1-5 CMPBO on Figure 1-5 3 2 3 3 GPIOB2 - 3 on Figure 1-4 LIMIT on Figure 1-3 TA0o, TA2o, TA3 o on Figure 1-3 Figure 1-6 56F8036 I/O Pin-Out Muxing (Part 4/5) 56F8036 Data Sheet, Rev.
Architecture Block Diagram To/From IPBus Bridge TA0o on Figure 1-6 (PWM) TA0 on Figure 1-6 (GPIOA6) T0o T0i T1o T1i TA1 on Figure 1-6 (GPIOB5) CMPAO on Figure 1-6 (CMPA) SYNC1 on Figure 1-3 (ADC) TMRA TA2o on Figure 1-6 (PWM) TA2 on Figure 1-6 (GPIOA4) T2o TA2 on Figure 1-5 (GPIOA8) T2i TA2 on Figure 1-4 (GPIOB2) CMPBO on Figure 1-6 (CMPB) SYNC0 on Figure 1-3 (ADC) TA3o on Figure 1-6 (PWM) TA3 on Figure 1-6 (GPIOA5) T3o TA3 on Figure 1-5 (GPIOA9) T3i TA3 on Figure 1-4 (GPIOB3) RELOAD on Figure
1.5 Product Documentation The documents listed in Table 1-1 are required for a complete description and proper design with the 56F8036. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, or online at: http://www.freescale.
Introduction Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F8036 are organized into functional groups, as detailed in Table 2-1. Table 2-2 summarizes all device pins. In Table 2-2, each table row describes the signal or signals present on a pin, sorted by pin number.
In Table 2-2, peripheral pins in bold identify reset state.
Introduction Table 2-2 56F8036 Pins (Continued) Peripherals: Pin # Pin Name 28 GPIOA8 GPIOA8, FAULT1, TA2, CMPAI1 29 GPIOA5 GPIOA5, PWM5, TA3, FAULT2 30 VSS VSS VSS 31 VDD VDD VDD 32 GPIOB0 GPIOB0, SCLK0, SCL B0 33 GPIOA4 GPIOA4, PWM4, TA2, FAULT1 A4 34 GPIOB9 GPIOB9, SDA, CANRX B9 Signal Name PWM Quad Timer Comp A8 FAULT1 TA2 CMPAI1 A5 PWM5 FAULT2 TA3 GPIO I2C SCL QSCI QSPI ADC MSCAN Power & Ground JTAG Misc SCLK0 PWM4 FAULT1 TA2 SDA CANRX 35 GPIOA2 G
VDD Power Ground Power Ground Other Supply Ports VSS VDDA VSSA VCAP 4 2 GPIOA4 (PWM4, TA2, FAULT1) 3 1 GPIOA5 (PWM5, TA3, FAULT2) 1 1 GPIOA6 (FAULT0, TA0) 1 1 56F8036 2 GPIOA0-3 (PWM0-3) GPIOA8 (FAULT1, TA2, CMPAI1) 1 GPIOA9 (FAULT2, TA3, CMPBI1) PWM or TMRA or CMP or QSPI or GPIOA 1 GPIOD4 (EXTAL) OSC Port or GPIO GPIOA10 (CMPAI2) 1 1 1 1 GPIOA11 (CMPBI2) GPIOD5 (XTAL, CLKIN) RESET or GPIOA RESET (GPIOA7) 1 GPIOB0 (SCLK0, SCL) QSPI or I2C or PWM or TMRA or GPIOB 1 GPIOB1 (SS0, S
56F8036 Signal Pins 2.2 56F8036 Signal Pins After reset, each pin is configured for its primary function (listed first). Any alternate functionality must be programmed. Table 2-3 56F8036 Signal and Package Information for the 48-Pin LQFP Signal Name LQFP Pin No. Type State During Reset Signal Description VDD 31 Supply Supply I/O Power — This pin supplies 3.3V power to the chip I/O interface. VDD 38 VSS 19 Supply Supply VSS — These pins provide ground for chip logic and I/O drivers.
Table 2-3 56F8036 Signal and Package Information for the 48-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOA0 44 (PWM0) Type Input/ Output State During Reset Input, internal pull-up enabled Output Signal Description Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. PWM0 — This is one of the six PWM output pins. After reset, the default state is GPIOA0.
56F8036 Signal Pins Table 2-3 56F8036 Signal and Package Information for the 48-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOA4 33 Type Input/ Output State During Reset Input, internal pull-up enabled Signal Description Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. (PWM4) Output PWM4 — This is one of the six PWM output pins.
Table 2-3 56F8036 Signal and Package Information for the 48-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOA6 26 (FAULT0) Type Input/ Output State During Reset Input, internal pull-up enabled Input Signal Description Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. Fault0 — This fault input pin is used for disabling selected PWM outputs in cases where fault conditions originate off-chip. (TA0) TA0 — Timer A, Channel 0.
56F8036 Signal Pins Table 2-3 56F8036 Signal and Package Information for the 48-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOA10 27 (CMPAI2) Type Input/ Output Input State During Reset Input, internal pull-up enabled Signal Description Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. Comparator A, Input 2 — This is an analog input to Comparator A. After reset, the default state is GPIOA10. The peripheral functionality is controlled via the SIM.
Table 2-3 56F8036 Signal and Package Information for the 48-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOB2 25 Type Input/ Output State During Reset Input, internal pull-up enabled Signal Description Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. (MISO0) Input/ Output QSPI0 Master In/Slave Out — This serial data pin is an input to a master device and an output from a slave device.
56F8036 Signal Pins Table 2-3 56F8036 Signal and Package Information for the 48-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOB5 4 Type Input/ Output State During Reset Input, internal pull-up enabled Signal Description Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. (TA1) Input/ Output (FAULT3) Input FAULT3 — This fault input pin is used for disabling selected PWM outputs in cases where fault conditions originate off-chip.
Table 2-3 56F8036 Signal and Package Information for the 48-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOB8 42 Type Input/ Output (SCL11) Input/ Output (CANTX12) Open Drain Output State During Reset Input, internal pull-up enabled Signal Description Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. Serial Clock 1 — This pin serves as the I2C serial clock. CAN Transmit Data — This is the SCAN interface output. After reset, the default state is GPIOB8.
56F8036 Signal Pins Table 2-3 56F8036 Signal and Package Information for the 48-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOC0 17 (ANA0 & CMPAI3) Type Input/ Output State During Reset Input Analog Input Signal Description Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANA0 — Analog input to ADC A, Channel 0. Comparator A, Input 3 — This is an analog input to Comparator A. When used as an analog input, the signal goes to both the ANA0 and CMPAI3.
Table 2-3 56F8036 Signal and Package Information for the 48-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOC4 8 (ANB0 & CMPBI3) Type Input/ Output State During Reset Input Analog Input Signal Description Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB0 — Analog input to ADC B, Channel 0. Comparator B, Input 3 — This is an analog input to Comparator B. When used an analog input, the signal goes to both the ANB0 and CMPBI3.
56F8036 Signal Pins Table 2-3 56F8036 Signal and Package Information for the 48-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOC12 7 (ANB4) Type Input/ Output State During Reset Input Analog Input Signal Description Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB4 — Analog input to ADC B, Channel 4. After reset, the default state is GPIOC12.
Table 2-3 56F8036 Signal and Package Information for the 48-Pin LQFP (Continued) Signal Name LQFP Pin No. Type TCK 21 Input (GPIOD2) State During Reset Input, internal pull-up enabled Input/ Output Signal Description Test Clock Input — This input pin provides a gated clock to synchronize the test logic and shift serial data to the JTAG/EOnCE port. The pin is connected internally to a pull-up resistor. A Schmitt trigger input is used for noise immunity.
Overview Part 3 OCCS 3.1 Overview The On-Chip Clock Synthesis (OCCS) module allows designers using an internal relaxation oscillator, an external crystal, or an external clock to run 56F8000 family devices at user-selectable frequencies up to 32MHz. For details, see the OCCS chapter in the 56F802X and 56F803XPeripheral Reference Manual. 3.
The 56F8000 family devices’ on-chip clock synthesis module has the following registers: • • • • • Control Register (OCCS_CTRL) Divide-by Register (OCCS_DIVBY) Status Register (OCCS_STAT) Shutdown Register (OCCS_SHUTDN) Oscillator Control Register (OCCS_OCTRL) For more information on these registers, please refer to the 56F802X and 56F803XPeripheral Reference Manual. 3.
Ceramic Resonator Crystal Frequency = 4 - 8MHz (optimized for 8MHz) EXTAL XTAL Rz EXTAL XTAL Rz Sample External Crystal Parameters: Rz = 750 KΩ Note: If the operating temperature range is limited to below 85oC (105oC junction), then Rz = 10 Meg Ω CL1 CL2 Figure 3-1 External Crystal Oscillator Circuit 3.6 Ceramic Resonator The internal crystal oscillator circuit is also designed to interface with a ceramic resonator in the frequency range of 4-8MHz.
56F8036 CLKMODE = 1 XTAL EXTAL External Clock GND or GPIO Figure 3-3 Connecting an External Clock Signal using XTAL 3.8 Alternate External Clock Input The recommended method of connecting an external clock is illustrated in Figure 3-3. The external clock source is connected to GPIO6/RXD (primary) or GPIOB5/TA1/FAULT3/XTAL/EXTAL (secondary). The user has the option of using GPIO6/RXD/CLKIN or GPIOB5/TA1/FAULT3/CLKIN as external clock input.
Interrupt Vector Table Table 4-1 Chip Memory Configurations On-Chip Memory 56F8036 Use Restrictions Program Flash (PFLASH) 32k x 16 or 64KB Erase / Program via Flash interface unit and word writes to CDBW Unified RAM (RAM) 4k x 16 or 8KB Usable by both the Program and Data memory spaces 4.2 Interrupt Vector Table Table 4-2 provides the 56F8036’s reset and interrupt priority structure, including on-chip peripherals.
Table 4-2 Interrupt Vector Table Contents1 (Continued) Peripheral Vector Number Priority Level Vector Base Address + Interrupt Function LVI 15 1-3 P:$1E Low-Voltage Detector (Power Sense) PLL 16 1-3 P:$20 Phase-Locked Loop FM 17 0-2 P:$22 FM Access Error Interrupt FM 18 0-2 P:$24 FM Command Complete FM 19 0-2 P:$26 FM Command, Data, and Address Buffers Empty MSCAN 20 0-2 P:$28 MSCAN Error MSCAN 21 0-2 P:$2a MSCAN Receive MSCAN 22 0-2 P:$2C MSCAN Transmit MSCAN 2
Program Map Table 4-2 Interrupt Vector Table Contents1 (Continued) Peripheral Vector Number Priority Level Vector Base Address + Interrupt Function ADC 60 0-2 P:$78 ADC Zero Crossing or Limit Error PWM 61 0-2 P:$7A Reload PWM PWM 62 0-2 P:$7C PWM Fault SWILP 63 -1 P:$7E SW Interrupt Low Priority 1. Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced from the vector table, providing only 19 bits of address. 2.
4.4 Data Map Table 4-4 Data Memory Map1 Begin/End Address Memory Allocation X:$FF FFFF X:$FF FF00 EOnCE 256 locations allocated X:$FF FEFF X:$01 0000 RESERVED X:$00 FFFF X:$00 F000 On-Chip Peripherals 4096 locations allocated X:$00 EFFF X:$00 8800 RESERVED X:$00 87FF X:$00 8000 RESERVED X:$00 7FFF X:$00 0800 RESERVED X:$00 07FF X:$00 0000 On-Chip Data RAM 8KB2 1. All addresses are 16-bit Word addresses. 2. This RAM is mapped into Program space starting at P: $00 8000; see Figure 4-1.
EOnCE Memory Map 4.5 EOnCE Memory Map Figure 4-5 lists all EOnCE registers necessary to access or control the EOnCE.
4.6 Peripheral Memory-Mapped Registers On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may be accessed with the same addressing modes used for ordinary Data memory, except all peripheral registers should be read or written using word accesses only. Table 4-6 summarizes base addresses for the set of peripherals on the 56F8036 device. Peripherals are listed in order of the base address.
Peripheral Memory-Mapped Registers Table 4-7 Quad Timer A Registers Address Map (TMRA_BASE = $00 F000) Register Acronym Address Offset Register Description TMRA0_COMP1 $0 Compare Register 1 TMRA0_COMP2 $1 Compare Register 2 TMRA0_CAPT $2 Capture Register TMRA0_LOAD $3 Load Register TMRA0_HOLD $4 Hold Register TMRA0_CNTR $5 Counter Register TMRA0_CTRL $6 Control Register TMRA0_SCTRL $7 Status and Control Register TMRA0_CMPLD1 $8 Comparator Load Register 1 TMRA0_CMPLD2 $9 Comp
Table 4-7 Quad Timer A Registers Address Map (Continued) (TMRA_BASE = $00 F000) Register Acronym Address Offset Register Description TMRA2_CMPLD1 $28 Comparator Load Register 1 TMRA2_CMPLD2 $29 Comparator Load Register 2 TMRA2_CSCTRL $2A Comparator Status and Control Register TMRA2_FILT $2B Input Filter Register Reserved TMRA3_COMP1 $30 Compare Register 1 TMRA3_COMP2 $31 Compare Register 2 TMRA3_CAPT $32 Capture Register TMRA3_LOAD $33 Load Register TMRA3_HOLD $34 Hold Register
Peripheral Memory-Mapped Registers Table 4-8 Analog-to-Digital Converter Registers Address Map (Continued) (ADC_BASE = $00 F080) Register Acronym Address Offset Register Description ADC_RSLT2 $E Result Register 2 ADC_RSLT3 $F Result Register 3 ADC_RSLT4 $10 Result Register 4 ADC_RSLT5 $11 Result Register 5 ADC_RSLT6 $12 Result Register 6 ADC_RSLT7 $13 Result Register 7 ADC_RSLT8 $14 Result Register 8 ADC_RSLT9 $15 Result Register 9 ADC_RSLT10 $16 Result Register 10 ADC_RSLT11
Table 4-8 Analog-to-Digital Converter Registers Address Map (Continued) (ADC_BASE = $00 F080) Register Acronym Address Offset Register Description ADC_OFFST6 $32 Offset Register 6 ADC_OFFST7 $33 Offset Register 7 ADC_PWR $34 Power Control Register ADC_CAL $35 Calibration Register Reserved Table 4-9 Pulse Width Modulator Registers Address Map (PWM_BASE = $00 F0C0) Register Acronym Address Offset Register Description PWM_CTRL $0 Control Register PWM_FCTRL $1 Fault Control Register PWM_
Peripheral Memory-Mapped Registers Table 4-10 Interrupt Control Registers Address Map (ITCN_BASE = $00 F0E0) Register Acronym Address Offset Register Description ITCN_IPR0 $0 Interrupt Priority Register 0 ITCN_IPR1 $1 Interrupt Priority Register 1 ITCN_IPR2 $2 Interrupt Priority Register 2 ITCN_IPR3 $3 Interrupt Priority Register 3 ITCN_IPR4 $4 Interrupt Priority Register 4 ITCN_IPR5 $5 Interrupt Priority Register 5 ITCN_IPR6 $6 Interrupt Priority Register 6 ITCN_VBA $7 Vector Bas
Table 4-11 SIM Registers Address Map (Continued) (SIM_BASE = $00 F100) Register Acronym Address Offset Register Description Reserved SIM_CLKOUT $A Clock Out Select Register SIM_PCR $B Peripheral Clock Rate Register SIM_PCE0 $C Peripheral Clock Enable Register 0 SIM_PCE1 $D Peripheral Clock Enable Register 1 SIM_SD0 $E Peripheral STOP Disable Register 0 SIM_SD1 $F Peripheral STOP Disable Register 1 SIM_IOSAHI $10 I/O Short Address Location High Register SIM_IOSALO $11 I/O Short Addr
Peripheral Memory-Mapped Registers Table 4-14 Power Supervisor Registers Address Map (PS_BASE = $00 F140) Register Acronym Address Offset Register Description PS_CTRL $0 Control Register PS_STAT $1 Status Register Reserved Table 4-15 GPIOA Registers Address Map (GPIOA_BASE = $00 F150) Register Acronym Address Offset Register Description GPIOA_PUPEN $0 Pull-up Enable Register GPIOA_DATA $1 Data Register GPIOA_DDIR $2 Data Direction Register GPIOA_PEREN $3 Peripheral Enable Register G
Table 4-17 GPIOC Registers Address Map (GPIOC_BASE = $00 F170) Register Acronym Address Offset Register Description GPIOC_PUPEN $0 Pull-up Enable Register GPIOC_DATA $1 Data Register GPIOC_DDIR $2 Data Direction Register GPIOC_PEREN $3 Peripheral Enable Register GPIOC_IASSRT $4 Interrupt Assert Register GPIOC_IEN $5 Interrupt Enable Register GPIOC_IEPOL $6 Interrupt Edge Polarity Register GPIOC_IPEND $7 Interrupt Pending Register GPIOC_IEDGE $8 Interrupt Edge-Sensitive Register
Peripheral Memory-Mapped Registers Table 4-20 Programmable Interval Timer 1 Registers Address Map (PIT1_BASE = $00 F1A0) Register Acronym Address Offset Register Description PIT1_CTRL $0 Control Register PIT1_MOD $1 Modulo Register PIT1_CNTR $2 Counter Register Table 4-21 Programmable Interval Timer 2 Registers Address Map (PIT2_BASE = $00 F1B0) Register Acronym Address Offset Register Description PIT2_CTRL $0 Control Register PIT2_MOD $1 Modulo Register PIT2_CNTR $2 Counter Register
Table 4-24 Comparator A Registers Address Map (CMPA_BASE = $00 F1E0) Register Acronym Address Offset Register Description CMPA_CTRL $0 Control Register CMPA_STAT $1 Status Register CMPA_FILT $2 Filter Register Table 4-25 Comparator B Registers Address Map (CMPB_BASE = $00 F1F0) Register Acronym Address Offset Register Description CMPB_CTRL $0 Control Register CMPB_STAT $1 Status Register CMPB_FILT $2 Filter Register Table 4-26 Queued Serial Communication Interface 0 Registers Address
Peripheral Memory-Mapped Registers Table 4-28 I2C Registers Address Map (I2C_BASE = $00 F280) Register Acronym Address Offset Register Description I2C_CTRL $0 Control Register I2C_TAR $2 Target Address Register I2C_SAR $4 Slave Address Register I2C_DATA $8 RX/TX Data Buffer and Command Register I2C_SSHCNT $A Standard Speed Clock SCL High Count Register I2C_SSLCNT $C Standard Speed Clock SCL Low Count Register I2C_FSHCNT $E Fast Speed Clock SCL High Count Register I2C_FSLCNT $10 Fa
Table 4-29 Flash Module Registers Address Map (FM_BASE = $00 F400) Register Acronym Address Offset Register Description FM_CLKDIV $0 Clock Divider Register FM_CNFG $1 Configuration Register $2 Reserved FM_SECHI $3 Security High Half Register FM_SECLO $4 Security Low Half Register $5 - $9 FM_PROT $10 Reserved Protection Register $11 - $12 Reserved FM_USTAT $13 User Status Register FM_CMD $14 Command Register $15 - $17 FM_DATA $18 Data Buffer Register $19 - $A FM_IFROPT_1 FM_TST
Peripheral Memory-Mapped Registers Table 4-30 MSCAN Registers Address Map (Continued) (MSCAN_BASE = $00 F800) Register Acronym Address Offset Register Description MSCAN_TXERR $0F Transmit Error Register MSCAN_IDAR0 $10 Identifier Acceptance Register 0 MSCAN_IDAR1 $11 Identifier Acceptance Register 1 MSCAN_IDAR2 $12 Identifier Acceptance Register 2 MSCAN_IDAR3 $13 Identifier Acceptance Register 3 MSCAN_IDMR0 $14 Identifier Mask Register 0 MSCAN_IDMR1 $15 Identifier Mask Register 1 MS
Table 4-30 MSCAN Registers Address Map (Continued) (MSCAN_BASE = $00 F800) Register Acronym Address Offset Register Description MSCAN_TXFG3 $33 Foreground Transmit Buffer 3 MSCAN_TXFG4 $34 Foreground Transmit Buffer 4 MSCAN_TXFG5 $35 Foreground Transmit Buffer 5 MSCAN_TXFG6 $36 Foreground Transmit Buffer 6 MSCAN_TXFG7 $37 Foreground Transmit Buffer 7 MSCAN_TXFG8 $38 Foreground Transmit Buffer 8 MSCAN_TXFG9 $39 Foreground Transmit Buffer 9 MSCAN_TXFG10 $3A Foreground Transmit Buffer
Functional Description 5.3.1 Normal Interrupt Handling Once the INTC has determined that an interrupt is to be serviced and which interrupt has the highest priority, an interrupt vector address is generated. Normal interrupt handling concatenates the Vector Base Address (VBA) and the vector number to determine the vector address, generating an offset into the vector table for each interrupt. 5.3.
When an interrupt occurs, its vector number is compared with the FIM0 and FIM1 register values. If a match occurs, and it is a level 2 interrupt, the ITCN handles it as a Fast Interrupt. The ITCN takes the vector address from the appropriate FIVALn and FIVAHn registers, instead of generating an address that is an offset from the VBA. The core then fetches the instruction from the indicated vector address and if it is not a JSR, the core starts its Fast Interrupt handling. 5.
Operating Modes 5.5 Operating Modes The ITCN module design contains two major modes of operation: • • Functional Mode The ITCN is in this mode by default. Wait and Stop Modes During Wait and Stop modes, the system clocks and the 56800E core are turned off. The ITCN will signal a pending IRQ to the System Integration Module (SIM) to restart the clocks and service the IRQ. An IRQ can only wake up the core if the IRQ is enabled prior to entering the Wait or Stop mode. 5.
Add.
Register Descriptions 5.6.1 Interrupt Priority Register 0 (IPR0) Base + $0 Read 15 14 13 PLL IPL Write RESET 0 0 12 11 10 0 0 0 0 LVI IPL 0 0 9 8 RX_REG IPL 0 0 7 6 TX_REG IPL 0 0 5 4 TRBUF IPL 0 0 3 2 BKPT_U IPL 0 0 1 0 STPCNT IPL 0 0 Figure 5-3 Interrupt Priority Register 0 (IPR0) 5.6.1.
5.6.1.5 EOnCE Transmit Register Empty Interrupt Priority Level (TX_REG IPL)— Bits 7–6 This field is used to set the interrupt priority level for the EOnCE Transmit Register Empty IRQ. This IRQ is limited to priorities 1 through 3. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3 5.6.1.
Register Descriptions 5.6.2 Interrupt Priority Register 1 (IPR1) Base + $1 Read 15 14 GPIOD IPL Write RESET 0 0 13 12 MSCAN_WK UP IPL 0 0 11 10 MSCAN_TX IPL 0 0 9 8 MSCAN_RX IPL 0 0 7 6 MSCAN_ERR IPL 0 0 5 4 FM_CBE IPL 0 0 3 2 FM_CC IPL 0 0 1 0 FM_ERR IPL 0 0 Figure 5-4 Interrupt Priority Register 1 (IPR1) 5.6.2.1 GPIOD Interrupt Priority Level (GPIOD IPL)—Bits 15–14 This field is used to set the interrupt priority level for the GPIOD IRQ.
5.6.2.4 MSCAN Receive Interrupt Priority Level (MSCAN_RX IPL)—Bits 9–8 This field is used to set the interrupt priority level for MSCAN Receive IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.2.5 MSCAN Error Interrupt Priority Level (MSCAN_ERR IPL)—Bits 7–6 This field is used to set the interrupt priority level for the MSCAN Error IRQ.
Register Descriptions 5.6.3 Interrupt Priority Register 2 (IPR2) Base + $2 Read 15 14 QSCI0_XMIT IPL Write RESET 0 0 13 12 11 10 0 0 0 0 0 0 0 0 9 8 QSPI0_XMIT IPL 0 0 7 6 QSPI0_RCV IPL 0 0 5 4 GPIOA IPL 0 0 3 2 GPIOB IPL 0 0 1 0 GPIOC IPL 0 0 Figure 5-5 Interrupt Priority Register 2 (IPR2) 5.6.3.
5.6.3.5 GPIOA Interrupt Priority Level (GPIOA IPL)—Bits 5–4 This field is used to set the interrupt priority level for the GPIOA IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.6 GPIOB Interrupt Priority Level (GPIOB IPL)—Bits 3–2 This field is used to set the interrupt priority level for the GPIOB IRQ.
Register Descriptions 5.6.4.2 Reserved—Bits 13–6 This bit field is reserved. Each bit must be set to 0. 5.6.4.3 QSCI 0 Receiver Full Interrupt Priority Level (QSCI0_RCV IPL)—Bits 5–4 This field is used to set the interrupt priority level for the QSCI0 Receiver Full IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4.
5.6.5.1 Timer A, Channel 3 Interrupt Priority Level (TMRA_3 IPL)— Bits 15–14 This field is used to set the interrupt priority level for the Timer A, Channel 3 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.5.
Register Descriptions I2C Status Interrupt Priority Level (I2C_STAT IPL)—Bits 7–6 5.6.5.5 This field is used to set the interrupt priority level for the I2C Status IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 I2C Transmit Interrupt Priority Level (I2C_TX IPL)—Bits 5–4 5.6.5.
5.6.6.1 Programmable Interval Timer 1 Interrupt Priority Level (PIT1 IPL)— Bits 15–14 This field is used to set the interrupt priority level for the Programmable Interval Timer 1 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.6.
Register Descriptions 5.6.7 Interrupt Priority Register 6 (IPR6) Base + $6 15 14 13 12 Read 0 0 0 0 0 0 0 0 Write RESET 11 10 PWM_F IPL 0 9 8 PWM_RL IPL 0 0 0 7 6 ADC_ZC IPL 0 0 5 4 ADCB_CC IPL 0 0 3 2 ADCA_CC IPL 0 0 1 0 PIT2 IPL 0 0 Figure 5-9 Interrupt Priority Register 6 (IPR6) 5.6.7.1 Reserved—Bits 15–12 This bit field is reserved. Each bit must be set to 0. 5.6.7.
5.6.7.5 ADC B Conversion Complete Interrupt Priority Level (ADCB_CC IPL)—Bits 5–4 This field is used to set the interrupt priority level for the ADC B Conversion Complete IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.7.
Register Descriptions 5.6.8.2 Vector Address Bus (VAB) Bits 13–0 The value in this register is used as the upper 14 bits of the interrupt vector VAB[20:0]. The lower 7 bits are determined based on the highest priority interrupt and are then appended onto VBA before presenting the full VAB to the Core. 5.6.
5.6.11 Fast Interrupt 0 Vector Address High Register (FIVAH0) Base + $A 15 14 13 12 11 10 9 8 7 6 5 Read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 2 1 0 FAST INTERRUPT 0 VECTOR ADDRESS HIGH Write RESET 3 0 0 0 0 0 Figure 5-13 Fast Interrupt 0 Vector Address High Register (FIVAH0) 5.6.11.1 Reserved—Bits 15–5 This bit field is reserved. Each bit must be set to 0. 5.6.11.
Register Descriptions 5.6.13.1 Fast Interrupt 1 Vector Address Low (FIVAL1)—Bits 15–0 The lower 16 bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAH1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register. 5.6.
5.6.16 IRQ Pending Register 1 (IRQP1) Base + $F 15 14 13 12 11 10 9 Read 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 PENDING[32:17] Write RESET 1 1 1 1 1 1 1 1 1 Figure 5-18 IRQ Pending Register 1 (IRQP1) 5.6.16.1 IRQ Pending (PENDING)—Bits 32–17 These register bit values represent the pending IRQs for interrupt vector numbers 17 through 32. Ascending IRQ numbers correspond to ascending bit locations.
Register Descriptions 5.6.19 Interrupt Control Register (ICTRL) $Base + $16 15 Read INT 14 13 12 11 10 IPIC 9 8 7 6 VAB Write RESET 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INT_ DIS 1 1 1 0 0 0 1 1 1 0 0 Figure 5-21 Interrupt Control Register (ICTRL) 5.6.19.1 Interrupt (INT)—Bit 15 This read-only bit reflects the state of the interrupt to the 56800E core. • • 0 = No interrupt is being sent to the 56800E core 1 = An interrupt is being sent to the 56800E core 5.6.19.
5.6.19.4 Interrupt Disable (INT_DIS)—Bit 5 This bit allows all interrupts to be disabled. • • 0 = Normal operation (default) 1 = All interrupts disabled 5.6.19.5 Reserved—Bits 4-2 This bit field is reserved. Each bit must be set to 1. 5.6.19.6 Reserved—Bits 1–0 This bit field is reserved. Each bit must be set to 0. 5.7 Resets 5.7.1 General Table 5-5 Reset Summary Reset Priority Core Reset 5.7.2 5.7.2.
Introduction 5.7.3 ITCN After Reset After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled, except the core IRQs with fixed priorities: • • • • • • • • Illegal Instruction SW Interrupt 3 HW Stack Overflow Misaligned Long Word Access SW Interrupt 2 SW Interrupt 1 SW Interrupt 0 SW Interrupt LP These interrupts are enabled at their fixed priority levels. Part 6 System Integration Module (SIM) 6.
• • • • • • • • Permits selected peripherals to run in Stop mode to generate Stop recovery interrupts Controls for programmable peripheral and GPIO connections Software chip reset I/O short address base location control Peripheral protection control to provide runaway code protection for safety-critical applications Controls output of internal clock sources to I/O pins Four general-purpose software control registers are reset only at power-on Peripherals Stop mode clocking control 56F8036 Data Sheet, Rev.
Register Descriptions 6.3 Register Descriptions A write to an address without an associated register is an NOP. A read from an address without an associated register returns unknown data. Table 6-1 SIM Registers (SIM_BASE = $00 F100) Register Acronym Base Address + Register Name Section Location CTRL $0 Control Register 6.3.1 RSTAT $1 Reset Status Register 6.3.2 SWC0 $2 Software Control Register 0 6.3.3 SWC1 $3 Software Control Register 1 6.3.3 SWC2 $4 Software Control Register 2 6.
Add.
Register Descriptions 6.3.1 SIM Control Register (SIM_CTRL) Base + $0 15 14 13 12 11 10 9 8 7 6 5 4 Read 0 0 0 0 0 0 0 0 0 0 ONCE EBL SW RST 0 0 0 0 0 0 0 0 0 0 0 0 Write RESET 3 2 1 0 STOP_ DISABLE WAIT_ DISABLE 0 0 0 0 Figure 6-2 SIM Control Register (SIM_CTRL) 6.3.1.1 Reserved—Bits 15–6 This bit field is reserved. Each bit must be set to 0. 6.3.1.
most recent reset source will be indicated if multiple resets occur. If multiple reset sources assert simultaneously, the highest-precedence source will be indicated. The precedence from highest to lowest is Power-On Reset, External Reset, COP Loss of Reference Reset, COP Time-Out Reset, and Software Reset.
Register Descriptions 6.3.3 SIM Software Control Registers (SIM_SWC0, SIM_SWC1, SIM_SWC2, and SIM_SWC3) These registers are general-purpose registers. They are reset only at power-on, so they can monitor software execution flow. Base + $2 15 14 13 12 11 10 Read 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 Software Control Data 0 - 3 Write RESET 0 0 0 0 0 0 0 0 0 0 Figure 6-4 SIM Software Control Register 0 (SIM_SWC0 - 3) 6.3.3.
6.3.6 SIM Power Control Register (SIM_PWR) This register controls the Standby mode of the large on-chip regulator. The large on-chip regulator derives the core digital logic power supply from the IO power supply. At a system bus frequency of 200kHz, the large regulator may be put in a reduced-power standby mode without interfering with device operation to reduce device power consumption.
Register Descriptions 6.3.7.1 Reserved—Bits 15–10 This bit field is reserved. Each bit must be set to 0. 6.3.7.2 • • PWM3—Bit 9 0 = Peripheral output function of GPIOA[3] is defined to be PWM3 1 = Peripheral output function of GPIOA[3] is defined to be the Relaxation Oscillator Clock 6.3.7.3 • • PWM2—Bit 8 0 = Peripheral output function of GPIOA[2] is defined to be PWM2 1 = Peripheral output function of GPIOA[2] is defined to be the system clock 6.3.7.
6.3.8.2 Quad Timer A Clock Rate (TMRA_CR)—Bit 14 This bit selects the clock speed for the Quad Timer A module. • • 0 = Quad Timer A clock rate equals the system clock rate, to a maximum 32MHz (default) 1 = Quad Timer A clock rate equals 3X system clock rate, to a maximum 96MHz 6.3.8.3 Pulse Width Modulator Clock Rate (PWM_CR)—Bit 13 This bit selects the clock speed for the PWM module.
Register Descriptions 6.3.9.2 • • 0 = The clock is not provided to the Comparator A module (the Comparator A module is disabled) 1 = The clock is enabled to the Comparator A module 6.3.9.3 • • Digital-to-Analog Clock Enable 1 (DAC1)—Bit 13 0 = The clock is not provided to the DAC1 module (the DAC1 module is disabled) 1 = The clock is enabled to the DAC1 module 6.3.9.
6.3.9.14 • • PWM Clock Enable (PWM)—Bit 0 0 = The clock is not provided to the PWM module (the PWM module is disabled) 1 = The clock is enabled to the PWM module 6.3.10 Peripheral Clock Enable Register 1 (SIM_PCE1) See Section 6.3.9 for general information about Peripheral Clock Enable registers.
Register Descriptions 6.3.10.9 • • Quad Timer A, Channel 0 Clock Enable (TA0)—Bit 0 0 = The clock is not provided to the Timer A0 module (the Timer A0 module is disabled) 1 = The clock is enabled to the Timer A0 module 6.3.11 Stop Disable Register 0 (SD0) By default, peripheral clocks are disabled during Stop mode in order to maximize power savings. This register will allow an individual peripheral to operate in Stop mode.
6.3.11.4 • • Digital-to-Analog Converter 0 Clock Stop Disable (DAC0_SD)—Bit 12 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register 6.3.11.5 Reserved—Bit 11 This bit field is reserved. It must be set to 0. 6.3.11.
Register Descriptions 6.3.11.14 PWM Clock Stop Disable (PWM_SD)—Bit 0 • • 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register 6.3.12 Stop Disable Register 1 (SD1) See Section 6.3.11 for general information about Stop Disable Registers.
6.3.12.7 • • 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1 register 6.3.12.8 • • Quad Timer A, Channel 1 Clock Stop Disable (TA1_SD)—Bit 1 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1 register 6.3.12.
Register Descriptions Base + $10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ISAL[23:22] Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Figure 6-15 I/O Short Address Location High Register (SIM_IOSAHI) 6.3.13.1 Reserved—Bits 15—2 This bit field is reserved. Each bit must be set to 0. 6.3.13.
Base + $12 15 14 13 12 11 10 9 8 7 6 5 4 Read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 1 PCEP Write RESET 2 0 0 GIPSP 0 0 0 Figure 6-17 Protection Register (SIM_PROT) 6.3.15.1 Reserved—Bits 15–4 This bit field is reserved. Each bit must be set to 0. 6.3.15.2 Peripheral Clock Enable Protection (PCEP)—Bits 3–2 These bits enable write protection of all fields in the PCEn, SDn, and PCR registers in the SIM module.
Register Descriptions GPIOA6_PEREN Register SIM_GPSA0 Register PWM FAULT0 GPIOA6 0 GPIOA6 pin 0 1 1 Timer A0 Figure 6-18 Overall Control of Signal Source Using SIM_GPSnn Control In some cases, the user can choose peripheral function between several I/O, each of which have the option to be programmed to control a specific peripheral function. If the user wishes to use that function, only one of these I/O must be configured to control that peripheral function.
6.3.16.3 Configure GPIOA5 (GPS_A5)—Bits 11–10 This field selects the alternate function for GPIOA5. • • • • 00 = PWM5 - PWM5 (default) 01 = FAULT2 - PWM FAULT2 Input 10 = TA3 - Timer A3 11 = Reserved 6.3.16.4 Configure GPIOA4 (GPS_A4)—Bits 9–8 This field selects the alternate function for GPIOA4. • • • • 00 = PWM4 - PWM4 (default) 01 = FAULT1 - PWM FAULT1 Input 10 = TA2 - Timer A2 11 = Reserved 6.3.16.5 Reserved—Bits 7–0 This bit field is reserved. Each bit must be set to 0. 6.3.
Register Descriptions 6.3.17.3 Configure GPIOA8 (GPS_A8)—Bits 1–0 This field selects the alternate function for GPIOA8. • • • • 00 = FAULT1 - PWM FAULT1 Input (default) 01 = TA2 - Timer A2 10 = CMPAI1 - Comparator A Input 1 11 = Reserved 6.3.18 SIM GPIO Peripheral Select Register 0 for GPIOB (SIM_GPSB0) See Section 6.3.16 for general information about GPIO Peripheral Select Registers.
6.3.18.5 Configure GPIOB3 (GPS_B3)—Bits 7–6 This field selects the alternate function for GPIOB3. • • • • 00 = MOSI0 - QSPI0 Master Out/Slave In (default) 01 = TA3 - Timer A3 10 = PSRC1 - PWM2 / PWM3 Pair External Source 11 = Reserved 6.3.18.6 Configure GPIOB2 (GPS_B2)—Bits 5–4 This field selects the alternate function for GPIOB2. • • • • 00 = MISO0 QSPI0 Master In/Slave Out (default) 01 = TA2 - Timer A2 10 = PSRC0 - PWM0 / PWM1 Pair External Source 11 = Reserved 6.3.18.
Register Descriptions 6.3.19.1 Reserved—Bits 15–5 This bit field is reserved. Each bit must be set to 0. 6.3.19.2 Configure GPIOB9 (GPS_B9)—Bit 4 This field selects the alternate function for GPIOB9. • • 0 = SDA - I2C Serial Data (default) 1 = CANRX - MSCAN Receive Data 6.3.19.3 Reserved—Bit 3 This bit field is reserved. It must be set to 0. 6.3.19.4 Configure GPIOB8 (GPS_B8)—Bit 2 This field selects the alternate function for GPIOB8.
6.3.20.2 Configure GPIOD5 (GPS_D5)—Bit 12 This field selects the alternate function for GPIOD5. • • 0 = XTAL - External Crystal Oscillator Output (default) 1 = CLKIN - External Clock Input 6.3.20.3 Reserved—Bits 11–0 This bit field is reserved. Each bit must be set to 0. 6.3.
Register Descriptions Base + $18 15 14 13 12 11 10 9 Read 0 0 IPS0_ FAULT2 0 IPS0_ FAULT1 0 0 0 0 0 0 0 0 0 Write RESET 8 7 6 5 IPS0_PSRC2 0 0 4 3 2 IPS0_PSRC1 0 0 0 1 0 IPS0_PSRC0 0 0 0 0 Figure 6-25 Internal Peripheral Source Select Register for PWM (SIM_IPS0) 6.3.21.1 Reserved—Bits 15–14 This bit field is reserved. Each bit must be set to 0. 6.3.21.
6.3.21.7 Select Input Peripheral Source for PWM2/PWM3 Pair Source (IPS0_PSRC1)—Bits 5–3 This field selects the alternate input peripheral source signal to feed PWM input PSRC1 as the PWM2/PWM3 pair source.
Register Descriptions Base + $19 15 14 13 12 11 10 9 8 7 Read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 4 0 0 3 0 IPS1_DSYNC1 Write RESET 5 0 0 2 1 0 IPS1_DSYNC0 0 0 0 Figure 6-26 Internal Peripheral Source Select Register for DACs (SIM_IPS1) 6.3.22.1 Reserved—Bits 15–7 This bit field is reserved. Each bit must be set to 0. 6.3.22.
Base + $1A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 IPS2_ TA3 0 0 0 IPS2_ TA2 0 0 0 IPS2_ TA1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write RESET Figure 6-27 Internal Peripheral Source Select Register for TMRA (SIM_IPS2) 6.3.23.1 Reserved—Bits 15–13 This bit field is reserved. Each bit must be set to 0. 6.3.23.
Clock Generation Overview 6.4 Clock Generation Overview The SIM uses the master clock (2X system clock) at a maximum of 64MHz from the OCCS module to produce a system clock at a maximum of 32MHz for the peripheral, core, and memory. It divides the master clock by two and gates it with appropriate power mode and clock gating controls.
6.5 Power-Saving Modes The 56F8036 operates in one of five Power-Saving modes, as shown in Table 6-2. Table 6-2 Clock Operation in Power-Saving Modes Mode Core Clocks Peripheral Clocks Description Run Core and memory clocks enabled Peripheral clocks enabled Device is fully functional Wait Core and memory clocks disabled Peripheral clocks enabled Core executes WAIT instruction to enter this mode. Typically used for power-conscious applications.
Resets default behavior of Stop mode. By asserting a peripheral’s Stop disable bit, the peripheral clock continues to operate in Stop mode. This is useful to generate interrupts which will recover the device from Stop mode to Run mode. Standby mode provides normal operation but at very low speed and power utilization. It is possible to invoke Stop or Wait mode while in Standby mode for even greater levels of power reduction.
EXTENDED_POR JTAG POR Power-On Reset (active low) pulse shaper Delay 64 OSC_CLK Clock Memory Subsystem CLKGEN_RST OCCS COMBINED_RST External RESET IN (active low) PERIP_RST Delay 32 OSC_CLK Clock RESET Peripherals pulse shaper Delay 32 sys clocks COP_TOR (active low) SW Reset pulse shaper COP_LOR (active low) Delay blocks assert immediately and deassert only after the programmed number of clock cycles.
Clocks The deassertion sequence of internal resets coordinates the device start up, including the clocking system start up. The sequence is described in the following steps: 1. As power is applied, the Relaxation Oscillator starts to operate. When a valid operating voltage is reached, the POR reset will release. 2. The release of POR reset permits operation of the POR reset extender. The POR extender generates an extended POR reset, which is released 64 OSC_CLK cycles after POR reset.
Maximum Delay = 64 OSC_CLK cycles for POR reset extension and 32 OSC_CLK cycles for Combined reset extension RST MSTR_OSC Switch on falling OSC_CLK 96 MSTR_OSC cycles CKGEN_RST 2X SYS_CLK SYS_CLK SYS_CLK_D SYS_CLK_DIV2 32 SYS_CLK cycles delay Switch on falling SYS_CLK PERIP_RST Switch on falling SYS_CLK 32 SYS_CLK cycles delay CORE_RST Figure 6-29 Timing Relationships of Reset Signal to Clocks 6.8 Interrupts The SIM generates no interrupts.
Flash Access Lock and Unlock Mechanisms execution is otherwise unaffected. 7.2 Flash Access Lock and Unlock Mechanisms There are several methods that effectively lock or unlock the on-chip flash. 7.2.1 Disabling EOnCE Access On-chip flash can be read by issuing commands across the EOnCE port, which is the debug interface for the 56800E CPU. The TCK, TMS, TDO, and TDI pins comprise a JTAG interface onto which the EOnCE port functionality is mapped.
The user is responsible for directing the device to invoke the flash programming subroutine to reprogram the word $0000 into program memory location $00 7FF7. This is done by, for example, toggling a specific pin or downloading a user-defined key through serial interfaces. Note: Flash contents can only be programmed for 1s to 0s. 7.3 Product Analysis The recommended method of unsecuring a secured device for product analysis of field failures is via the method described in section 7.2.4.
Configuration Table 8-2 GPIO External Signals Map GPIO Function Peripheral Function LQFP Package Pin Notes GPIOA0 PWM0 44 Defaults to A0 GPIOA1 PWM1 43 Defaults to A1 GPIOA2 PWM2 35 Defaults to A2 GPIOA3 PWM3 36 Defaults to A3 GPIOA4 PWM4 / TA2 / FAULT1 33 SIM register SIM_GPS is used to select between PWM4, TA2, and FAULT1. Defaults to A4 GPIOA5 PWM5 / TA3 / FAULT2 29 SIM register SIM_GPS is used to select between PWM5, TA3, and FAULT2.
Table 8-2 GPIO External Signals Map (Continued) GPIO Function Peripheral Function LQFP Package Pin Notes GPIOB3 MOSI0 / TA3 / PSRC1 24 SIM register SIM_GPS is used to select between MOSI0, TA3 and PSRC1. Defaults to B3 GPIOB5 TA1 / FAULT3 / CLKIN 4 SIM register SIM_GPS is used to select between TA1, FAULT3, and CLKIN. CLKIN functionality is enabled using the PLL Control Register within the OCCS block.
Reset Values Table 8-2 GPIO External Signals Map (Continued) GPIO Function Peripheral Function LQFP Package Pin Notes GPIOC5 ANB1 9 Defaults to C5 GPIOC6 ANB2 / VREFHB 10 SIM register SIM_GPS is used to select between ANB2 and VREFHB. Defaults to C6 GPIOC7 ANB3 / VREFLB 11 SIM register SIM_GPS is used to select between ANB3 and VREFLB.
Add. Offset Register Acronym $0 GPIOA_PUPEN $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B GPIOA_DATA GPIOA_DDIR GPIOA_PEREN GPIOA_IASSRT GPIOA_IEN GPIOA_IEPOL GPIOA_IPEND GPIOA_IEDGE GPIOA_PPOUTM GPIOA_RDATA GPIOA_DRIVE 15 14 13 12 R W RS 0 0 0 0 0 1 1 1 R W RS .0 .0 .0 .0 0 0 0 0 . 0. .0. . 0. 0 0 0 R . 0.
Reset Values Add.
Add.
Reset Values Add.
Part 9 Joint Test Action Group (JTAG) 9.1 56F8036 Information Please contact your Freescale sales representative or authorized distributor for device/package-specific BSDL information. The TRST pin is not available in this package. The pin is tied to VDD in the package. The JTAG state machine is reset during POR and can also be reset via a soft reset by holding TMS high for five rising edges of TCK, as described in the 56F802X and 56F803XPeripheral Reference Manual. Part 10 Specifications 10.
General Characteristics Table 10-1 Absolute Maximum Ratings (VSS = 0V, VSSA = 0V) Characteristic Symbol Notes Min Max Unit Supply Voltage Range VDD -0.3 4.0 V Analog Supply Voltage Range VDDA - 0.3 4.0 V ADC High Voltage Reference VREFHx - 0.3 4.0 V Voltage difference VDD to VDDA ΔVDD - 0.3 0.3 V Voltage difference VSS to VSSA ΔVSS - 0.3 0.3 V Digital Input Voltage Range VIN Pin Groups 1, 2 - 0.3 6.0 V Oscillator Voltage Range VOSC Pin Group 4 - 0.4 4.
10.1.
General Characteristics Table 10-4 Recommended Operating Conditions (VREFL x= 0V, VSSA = 0V, VSS = 0V) Characteristic Min Typ Max Unit VDD, VDDA 3 3.3 3.6 V VREFHx 3.0 VDDA V Voltage difference VDD to VDDA ΔVDD -0.1 0 0.1 V Voltage difference VSS to VSSA ΔVSS -0.1 0 0.
10.2 DC Electrical Characteristics Table 10-5 DC Electrical Characteristics At Recommended Operating Conditions Symbol Notes Min Typ Max Unit Test Conditions Output Voltage High VOH Pin Group 1 2.4 — — V IOH = IOHmax Output Voltage Low VOL Pin Groups 1, 2 — — 0.4 V IOL = IOLmax Digital Input Current High (a) pull-up enabled or disabled IIH Pin Groups 1, 2 — 0 +/- 2.5 μA VIN = 2.4V to 5.
DC Electrical Characteristics 2.0 0.0 µA - 2.0 - 4.0 - 6.0 - 8.0 - 10.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Volt Figure 10-1 IIN/IOZ vs. VIN (Typical; Pull-Up Disabled) Table 10-6 Current Consumption per Power Supply Pin Typical @ 3.3V, 25°C Mode Maximum@ 3.6V, 25°C Conditions IDD1 IDDA IDD1 IDDA RUN 32MHz Device Clock Relaxation Oscillator on PLL powered on Continuous MAC instructions with fetches from Program Flash All peripheral modules enabled.
Table 10-6 Current Consumption per Power Supply Pin (Continued) Typical @ 3.3V, 25°C Mode Maximum@ 3.
AC Electrical Characteristics capacitors tend to provide better performance tolerances. The output voltage can be measured directly on the VCAP pin. The specifications for this regulator are shown in Table 10-8. Table 10-8. Regulator Parameters Characteristic Short Circuit Current Short Circuit Tolerance (VCAP shorted to ground) Symbol Min Typical Max Unit ISS — 450 650 mA TRSC — — 30 minutes 10.
Table 10-9 Flash Timing Parameters Characteristic Symbol Min Typ Max Unit Program time1 Tprog 20 — 40 μs Erase time 2 Terase 20 — — ms Tme 100 — — ms Mass erase time 1. There is additional overhead which is part of the programming sequence. See the 56F802X and 56F803XPeripheral Reference Manual for details. 2. Specifies page erase time. There are 512 bytes per page in the Program Flash memory. 10.
Phase Locked Loop Timing 10.6 Phase Locked Loop Timing Table 10-11 PLL Timing Characteristic Symbol Min Typ Max Unit External reference crystal frequency for the PLL1 fosc 4 8 — MHz Internal reference relaxation oscillator frequency for the PLL frosc — 8 — MHz PLL output frequency2 (24 x reference frequency) fop 96 192 — MHz PLL lock time3 tplls — 40 100 µs Accumulated jitter using an 8MHz external crystal as the PLL source4 JA — — 0.
8.16 8.08 MHz 8 7.92 7.84 -50 -25 0 25 50 75 100 125 150 175 Degrees C (Junction) Figure 10-5 Relaxation Oscillator Temperature Variation (Typical) After Trim 56F8036 Data Sheet, Rev.
Reset, Stop, Wait, Mode Select, and Interrupt Timing 10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing Note: All address and data buses described here are internal.
10.9 Serial Peripheral Interface (SPI) Timing Table 10-14 SPI Timing1 Characteristic Symbol Cycle time Master Slave Min Max Unit 125 62.5 — — ns ns — 31 — — ns ns — 125 — — ns ns 50 31 — — ns ns 50 31 — — ns ns 20 0 — — ns ns 0 2 — — ns ns 4.8 15 ns 3.7 15.2 ns — — 4.5 20.4 ns ns 0 0 — — ns ns — — 11.5 10.0 ns ns — — 9.7 9.
Serial Peripheral Interface (SPI) Timing SS SS is held High on master (Input) tC tR tF tCL SCLK (CPOL = 0) (Output) tCH tF tR tCL SCLK (CPOL = 1) (Output) tDH tCH tDS MISO (Input) MSB in Bits 14–1 tDI MOSI (Output) LSB in tDI(ref) tDV Master MSB out Bits 14–1 Master LSB out tR tF Figure 10-7 SPI Master Timing (CPHA = 0) SS (Input) SS is held High on master tC tF tR tCL SCLK (CPOL = 0) (Output) tCH tF tCL SCLK (CPOL = 1) (Output) tCH tDS tR MISO (Input) MSB in Bits 14–1
SS (Input) tC tF tCL SCLK (CPOL = 0) (Input) tELG tR tCH tELD tCL SCLK (CPOL = 1) (Input) tCH tA MISO (Output) Slave MSB out tF tR Bits 14–1 tDS Slave LSB out tDV tDI tDH MOSI (Input) MSB in tD Bits 14–1 tDI LSB in Figure 10-9 SPI Slave Timing (CPHA = 0) SS (Input) tF tC tR tCL SCLK (CPOL = 0) (Input) tCH tELG tELD tCL SCLK (CPOL = 1) (Input) tDV tCH tR tA MISO (Output) Slave MSB out Bits 14–1 tDS tDV tDH MOSI (Input) tD tF MSB in Bits 14–1 Slave LSB out tD
Quad Timer Timing 10.10 Quad Timer Timing Table 10-15 Timer Timing1, 2 Characteristic Symbol Min Max Unit See Figure PIN 2T + 6 — ns 10-11 Timer input high / low period PINHL 1T + 3 — ns 10-11 Timer output period POUT 125 — ns 10-11 POUTHL 50 — ns 10-11 Timer input period Timer output high / low period 1. In the formulas listed, T = the clock cycle. For 32MHz operation, T = 31.25ns. 2. Parameters listed are guaranteed by design.
10.11 Serial Communication Interface (SCI) Timing Table 10-16 SCI Timing1 Characteristic Symbol Min Max Unit See Figure BR — (fMAX/16) Mbps — RXD3 Pulse Width RXDPW 0.965/BR 1.04/BR ns 10-12 TXD4 Pulse Width TXDPW 0.965/BR 1.
Freescale’s Scalable Controller Area Network (MSCAN) Timing 10.12 Freescale’s Scalable Controller Area Network (MSCAN) Timing Table 10-17 MSCAN Timing1 Characteristic Baud rate Bus wake-up detection Symbol Min Max Unit BRCAN — 1 Mbps TWAKEUP TIPBUS — µs 1. Parameters listed are guaranteed by design MSCAN_RX CAN receive data pin (Input) TWAKEUP Figure 10-14 Bus Wake-up Detection 10.
Table 10-18 I2C Timing (Continued) Standard Mode Characteristic Fast Mode Symbol Unit Minimum Maximum Minimum Maximum Rise time of both SDA and SCL signals tr — 1000 20 +0.1Cb5 300 ns Fall time of both SDA and SCL signals tf — 300 20 +0.1Cb5 300 ns Set-up time for STOP condition tSU; STO 4.0 — 0.6 — μs Bus free time between STOP and START condition tBUF 4.7 — 1.3 — μs Pulse width of spikes that must be suppressed by the input filter tSP N/A N/A 0 50 ns 1.
JTAG Timing 10.14 JTAG Timing Table 10-19 JTAG Timing Characteristic Symbol Min Max Unit See Figure TCK frequency of operation1 fOP DC SYS_CLK/8 MHz 10-16 TCK clock pulse width tPW 50 — ns 10-16 TMS, TDI data set-up time tDS 5 — ns 10-17 TMS, TDI data hold time tDH 5 — ns 10-17 TCK low to TDO data valid tDV — 30 ns 10-17 TCK low to TDO tri-state tTS — 30 ns 10-17 1. TCK frequency of operation must be less than 1/8 the processor rate.
10.15 Analog-to-Digital Converter (ADC) Parameters Table 10-20 ADC Parameters1 Parameter Symbol Min Typ Max Unit Resolution RES 12 — 12 Bits ADC internal clock fADIC 0.1 — 5.
Equivalent Circuit for ADC Inputs 10.16 Equivalent Circuit for ADC Inputs Figure 10-18 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time that S3 is closed/open. When S1/S2 are closed and S3 is open, one input of the sample and hold circuit moves to (VREFHx - VREFLx) / 2, while the other charges to the analog input voltage.
10.18 Digital-to-Analog Converter (DAC) Parameters Table 10-22 DAC Parameters Parameter Conditions/Comments Symbol Min Typ Max Unit 12 bits DC Specifications Resolution 12 Conversion time Conversion rate Power-up time Time from release of PWRDWN signal until DACOUT signal is valid TBD — 2 µS TBD — 500.000 conv/sec tDAPU — — 11 µS Accuracy Integral non-linearity1 Range of input digital words: 410 to 3891 ($19A - $F33) 5% to 95% of full range INL — +/- 3 +/- 8.
Power Consumption 10.19 Power Consumption See Section 10.1 for a list of IDD requirements for the 56F8036. This section provides additional detail which can be used to optimize power consumption for a given application.
Because of the low duty cycle on most device pins, power dissipation due to capacitive loads was found to be fairly low when averaged over a period of time. E, the external [static component], reflects the effects of placing resistive loads on the outputs of the device. Sum the total of all V2/R or IV to arrive at the resistive load contribution to power. Assume V = 0.5 for the purposes of these rough calculations. For instance, if there is a total of eight PWM outputs driving 10mA into LEDs, then P = 8*.
56F8036 Package and Pin-Out Information Part 11 Packaging 11.1 56F8036 Package and Pin-Out Information VCAP VDD VSS ORIENTATION MARK GPIOB6 / RXD0 / SDA / CLKIN GPIOA3 / PWM3 GPIOB1 / SS0 / SDA GPIOB7 / TXD0 / SCL GPIOD5 / XTAL / CLKIN GPIOD4 / EXTAL GPIOB8 / SCL / CANTX GPIOA1 / PWM1 GPIOA0 / PWM0 TDI / GPIOD0 GPIOB11 / CMPBO TMS / GPIOD3 TDO / GPIOD1 This section contains package and pin-out information for the 56F8036. This device comes in a 48-pin Low-profile Quad Flat Pack (LQFP).
Table 11-1 56F8036 48-Pin LQFP Package Identification by Pin Number1 Pin # Signal Name Pin # Signal Name Pin # Signal Name Pin # Signal Name 1 GPIOB6 RXD0 / SDA / CLKIN 13 VSSA 25 GPIOB2 MISO0 / TA2 / PSRC0 37 VCAP 2 GPIOB1 SS0 / SDA 14 GPIOC3 ANA3 / VREFLA 26 GPIOA6 FAULT0 / TA0 38 VDD 3 GPIOB7 TXD0 / SCL 15 GPIOC2 ANA2 / VREFHA 27 GPIOA10 CMPAI2 39 VSS 4 GPIOB5 TA1 / FAULT3 / CLKIN 16 GPIOC1 ANA1 28 GPIOA8 FAULT1 / TA2 / CMPAI1 40 GPIOD5 XTAL / CLKIN 5 GPIOA9 FAULT
56F8036 Package and Pin-Out Information 4X 0.200 AB T-U Z DETAIL Y A P A1 48 37 1 36 T U B V AE B1 12 25 13 AE V1 24 Z S1 DIM A A1 B B1 C D E F G H J K L M N P R S S1 V V1 W AA T, U, Z S DETAIL Y 4X 0.200 AC T-U Z 0.080 AC G AB AD AC M° BASE METAL TOP & BOTTOM R J 0.250 N MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.170 0.270 1.350 1.450 0.170 0.230 0.500 BSC 0.050 0.150 0.090 0.200 0.500 0.700 0 ° 7° 12 ° REF 0.090 0.160 0.250 BSC 0.150 0.
Part 12 Design Considerations 12.1 Thermal Design Considerations An estimation of the chip junction temperature, TJ, can be obtained from the equation: TJ = TA + (RθJΑ x PD) where: TA = Ambient temperature for the package (oC) RθJΑ = Junction-to-ambient thermal resistance (oC/W) PD = Power dissipation in the package (W) The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal performance.
Electrical Design Considerations The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction.
• Take special care to minimize noise levels on the VREF, VDDA, and VSSA pins • Using separate power planes for VDD and VDDA and separate ground planes for VSS and VSSA are recommended. Connect the separate analog and digital power and ground planes as close as possible to power supply outputs. If both analog circuit and digital circuit are powered by the same power supply, it is advisable to connect a small inductor or ferrite bead in serial with both VDDA and VSSA traces.
Electrical Design Considerations Part 14 Appendix Register acronyms are revised from previous device data sheets to provide a cleaner register description. A cross reference to legacy and revised acronyms are provided in the following table. Note: This table comprises all peripherals used in the 56F803x and 56F802x family; some of the peripherals described here may not be present on this device.
Table 14-1 Legacy and Revised Acronyms (Continued) Peripheral Reference Manual Data Sheet Register Name New Acronym Legacy Acronym New Acronym Legacy Acronym Processor Expert Acronym Memory Address Start End Computer Operating Properly (COP) Module Control Register CTRL COPCTL COP_CTRL COPCTL COPCTL 0XF120 Timeout Register TOUT COPTO COP_TOUT COPTO COPTO 0XF121 Counter Register CNTR COPCTR COP_CNTR COPCTR COPCTR 0XF122 56F8036 Data Sheet, Rev.
Electrical Design Considerations Table 14-1 Legacy and Revised Acronyms (Continued) Peripheral Reference Manual Data Sheet Register Name New Acronym Legacy Acronym New Acronym Legacy Acronym Processor Expert Acronym Memory Address Start End Inter-Integrated Circuit Interface (I2C) Module Control Register CTRL I2C_CTRL I2C_IBCR I2C_IBCR 0xF280 Target Address Register TAR IBCR I2C_TAR I2CTAR I2C_TAR 0xF282 Slave Address Register SAR I2C_SAR I2CSAR I2C_SAR 0xF242 Data Buffer & Comm
Table 14-1 Legacy and Revised Acronyms (Continued) Peripheral Reference Manual Data Sheet Register Name New Acronym Clear Activity Interrupt Register Legacy Acronym New Acronym Legacy Acronym Processor Expert Acronym Memory Address Start End CLRACT I2C_CLRACTIVITY I2C_CLRACTIVITY 0xF2AE Clear Stop Detect Interrupt Register CLRSTPDET I2C_CLR_STOPDET I2C_CLR_STOPDET 0xF2B0 Clear Start Detect Interrupt Register CLRSTDET I2C_CLR_STAR_DET I2C_CLR_STAR_DET 0xF2B2 Clear General Call Interrup
Electrical Design Considerations Table 14-1 Legacy and Revised Acronyms (Continued) Peripheral Reference Manual Data Sheet Register Name User Status Register New Acronym Legacy Acronym New Acronym Legacy Acronym Processor Expert Acronym Memory Address Start End USTAT FMUSTAT FM_USTAT FMUSTAT FMUSTAT 0xF413 Command Register CMD FMCMD FM_CMD FMCMD FMCMD 0xF414 Data Buffer Register DATA FMDATA FM_DATA FMDATA FMDATA 0xF418 Info Optional Data 1 Register OPT1 FMOPT1 FM_OPT1 FMO
Table 14-1 Legacy and Revised Acronyms (Continued) Peripheral Reference Manual Data Sheet Register Name New Acronym Legacy Acronym New Acronym Legacy Acronym Processor Expert Acronym Memory Address Start End Pulse Width Modulator (PWM) Module Control Register CTRL PMCTL Fault Control Register FCTRL Fault Status/Acknowledge Regis.
Electrical Design Considerations Table 14-1 Legacy and Revised Acronyms (Continued) Peripheral Reference Manual Data Sheet Register Name New Acronym Legacy Acronym New Acronym Legacy Acronym Processor Expert Acronym Memory Address Start End Transmitter Message Abort Acknowledge Register TAAK CAN_TAAK CANTAAK 0XF809 Transmitter FIFO Selection Register TBSEL CAN_TBSEL CANTBSEL 0XF80A Identifier Acceptance Control Register IDAC CAN_IDAC CANIDAC 0XF80B Miscellaneous Register MISC CAN_
Table 14-1 Legacy and Revised Acronyms (Continued) Peripheral Reference Manual Data Sheet Register Name New Acronym Legacy Acronym New Acronym Legacy Acronym Processor Expert Acronym Memory Address Start End Queued Serial Communications Interface (QSCI) Module n = 0, 1 Baud Rate Register RATE QSCI_RATE QSCI_SCIBR 0xF2n0 Control 1 Register CTRL1 QSCI_CTRL1 QSCI_SCICR 0xF2n1 Control 2 Register CTRL2 QSCI_CTRL2 QSCI_SCICR2 0xF2n2 Status Register STAT QSCI_STAT QSCI_SCISR 0xF2n3 Dat
Electrical Design Considerations Table 14-1 Legacy and Revised Acronyms (Continued) Peripheral Reference Manual Register Name New Acronym Legacy Acronym Memory Address Data Sheet New Acronym Legacy Acronym Processor Expert Acronym Start End Programmable Interval Timer (PIT) Module n = 0, 1, 2 Control Register CTRL PITn_CTRL PITCTRL0-2 PITn_CTRL 0xF1n0 Modulo Register MOD PITn_MOD PITMOD0-2 PITn_MOD 0xF1n1 Counter Register CNTR PITn_CNTR PITCNTR0-2 PITn_CNTR 0xF1n2 Control Register
Table 14-1 Legacy and Revised Acronyms (Continued) Peripheral Reference Manual Data Sheet Register Name New Acronym Legacy Acronym New Acronym Legacy Acronym Processor Expert Acronym Memory Address Start End 0XF060 0XF064 Interrupt Controller (ITCN) Module Interrupt Priority 0-4 Registers N/A N/A ITCN_IPR0-4 ITCN_IPR0-4 INTC_IPR0-4 Vector Base Address Register N/A N/A ITCN_VBA ITCN_VBA INTC_VBA 0XF065 Fast Interrupt Match 0 Register N/A N/A ITCN_FIM0 ITCN_FIM0 INTC_FIM0 0XF066
Electrical Design Considerations Table 14-1 Legacy and Revised Acronyms (Continued) Peripheral Reference Manual Data Sheet Register Name Processor Expert Acronym Memory Address New Acronym Legacy Acronym New Acronym Legacy Acronym I/O Short Address Location High Register N/A N/A SIM_ISALH SIM_ISALH SIM_ISALH 0xF110 I/O Short Address Location Low Register N/A N/A SIM_ISALL SIM_ISALL SIM_ISALL 0xF111 Protection Register N/A N/A SIM_PROT SIM_PROT SIM_PROT 0xF112 GPIOA Peripheral
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