Datasheet

56F8036 Data Sheet, Rev. 6
160 Freescale Semiconductor
Queued Serial Communications Interface (QSCI) Module
n = 0, 1
Baud Rate Register RATE QSCI_RATE QSCI_SCIBR 0xF2n0
Control 1 Register CTRL1 QSCI_CTRL1 QSCI_SCICR 0xF2n1
Cont r ol 2 Re giste r CTRL2 QSCI_CTRL2 QSCI_SCICR2 0xF 2n2
Status Register STAT QSCI_STAT QSCI_SCISR 0xF2n3
Data Register DATA QSCI_DATA QSCI_SCIDR 0xF2n4
Queued Serial Peripheral Interface (QSPI) Module
Status and Control
Register
SCTRL QSPI_SCTRL QSPI_SPSCR 0xF2n0
Data Size and Control
Register
DSCTRL QSPI_DSCTRL QSPI_SPDSR 0xF2n1
Data Receive
Register
DRCV QSPI_DRCV QSPI_SPDRR 0xF 2n2
Data Transmit
Register
DXMIT QSPI_DXMIT QSPI_SPDTR 0xF2n3
FIF O Contr ol Re gister FIFO QSPI_FIFO QSPI_SPFIFO 0 x F2n4
Wait Register WAIT QSPI_WAIT QSPI_SPWAIT 0xF2n5
Quad-Timer (TMR) Module
n = 0, 1, 2, 3
Compare 1 Register COMP1 TMRCMP1 TMRn_COMP1 TMRn_CMP1 TMRn_CMP1 0 xF0n0
Compare 2 Register COMP2 TMRCMP2 TMRn_COMP2 TMRn_CMP2 TMRn_CMP2 0xF0n1
Capture Register CAPT TMRCAP TMRn_CAPT TMRn_CAP TMRn_CAP 0xF 0n2
Load Register LOAD TMRLOAD TMRn_LOAD TMRn_LOAD TMRn_LOAD 0xF0n3
Hold Register HOLD TMRHOLD TMRn_HOLD TMRn_HOLD TMRn_HOLD 0 xF0n4
Counter Register CNTR TMRCNTR TMRn_CNTR TMRn_CNTR TMRn_CNTR 0xF0n5
Cont rol Re g ister CTRL TMRCTRL TMRn_CTRL TMRn_CTRL TMRn_CTRL 0 xF0n6
Status and Control
Register
SCTRL TMRSCR TMRn_SCTRL TMRn_SCR TMRn_SCR 0xF0n7
Comparator Load 1
Register
CMPLD1 TMRCMPLD1 TMRn_CMPLD1 TMRn_CMPLD1 TMRn_CMPLD1 0xF 0n8
Comparator Load 2
Register
CMPLD2 TMRCMPLD2 TMRn_CMPLD2 TMRn_CMPLD2 TMRn_CMPLD2 0xF0n9
Comparator
Status/Control
Register
CSCTRL TMRCOMSCR TMRn_CSCTRL TMRn_COMSCR TMRn_COMSCR 0xF 0nA
Input Filter Register FILT TMRn_FILT TMRn_FILT TMRn_FILT 0xF0nB
Enable Register ENBL TMRn_ENBL TMRn_ENBL TMRn_ENBL 0xF0nF
Voltage Regulator (VREG) Module
See SIM section
Table 14-1 Legacy and Revised Acronyms (Continued)
Register Name
Peripheral Reference
Manual
Data Sheet
Processor Expert
Acronym
Memory
Address
New
Acronym
Legacy
Acronym
New
Acronym
Legacy
Acronym
Start End