Datasheet

56F8036 Data Sheet, Rev. 6
Freescale Semiconductor 3
56F8036 Block Diagram
Programmable
Interval
Timer
Program Controller
and Hardware
Looping Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Address
Generation Unit
Bit
Manipulation
Unit
16-Bit
56800E Core
Interrupt
Controller
4
Unified Data /
Program RAM
4K x 16
PDB
PDB
XAB1
XAB2
XDB2
CDBR
QSPI
or PWM
or I
2
C
or TMRA
or GPIOB
IPBus Bridge (IPBB)
System Bus
Control
R/W Control
Memory
PAB
PAB
CDBW
CDBR
CDBW
JTAG/EOnCE
Port or
GPIOD
Digital Reg
Analog Reg
Low-Voltage
Supervisor
V
CAP
V
DD
V
SS
V
DDA
V
SSA
4
RESET or
GPIOA
AD0
5
Clock
Generator*
System
Integration
Module
P
O
R
O
S
C
PWM
or TMRA or CMP
or GPIOA
*Includes On-Chip
Relaxation Oscillator
COP/
Watchdog
AD1
5
Program Memory
32K x 16 Flash
ADC
or CMP
or GPIOC
QSCI
or PWM
or I
2
C
or TMRA
or GPIOB
3
3
4
2
XTAL, CLKIN, or
GPIOD
EXTAL or GPIOD
2
11
I
2
C
or CAN
or CMP
or GPIOB
DAC
• Up to 32 MIPS at 32MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 64KB (32K x 16) Program Flash
• 8KB (4K x 16) Unified Data/Program RAM
• One 6-channel PWM module clocked at up to 96MHz
• Two independent 5-channel 12-bit high-speed
Analog-to-Digital Converters (ADCs)
• Two internal 12-bit Digital-to-Analog Converters
(DACs)
• Two Analog Comparators
• Three Programmable Interval Timers (PITs)
• One Queued Serial Communication Interface (QSCI)
with LIN slave functionality
• One Queued Serial Peripheral Interface (QSPI)
• Freescale’s scalable controller area network (MSCAN)
2.0 A/B Module
• One 16-bit Quad Timer clocked at up to 96MHz
• One Inter-Integrated Circuit (I
2
C) port
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• Integrated Power-On Reset (POR) and Low-Voltage
Interrupt (LVI) module
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 39 GPIO lines
• 48-pin LQFP Package
56F8036 General Description