Datasheet

56F8036 Data Sheet, Rev. 6
42 Freescale Semiconductor
4.6 Peripheral Memory-Mapped Registers
On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may
be accessed with the same addressing modes used for ordinary Data memory, except all peripheral
registers should be read or written using word accesses only.
Table 4-6 summarizes base addresses for the set of peripherals on the 56F8036 device. Peripherals are
listed in order of the base address.
The following tables list all of the peripheral registers required to control or access the peripherals.
Table 4-6 Data Memory Peripheral Base Address Map Summary
Peripheral Prefix Base Address Table Number
Timer A TMRA X:$00 F000 4-7
ADC ADC X:$00 F080 4-8
PWM PWM X:$00 F0C0 4-9
ITCN ITCN X:$00 F0E0 4-10
SIM SIM X:$00 F100 4-11
COP COP X:$00 F120 4-12
CLK, PLL, OSC OCCS X:$00 F130 4-13
Power Supervisor PS X:$00 F140 4-14
GPIO Port A GPIOA X:$00 F150 4-15
GPIO Port B GPIOB X:$00 F160 4-16
GPIO Port C GPIOC X:$00 F170 4-17
GPIO Port D GPIOD X:$00 F180 4-18
PIT 0 PIT0 X:$00 F190 4-19
PIT 1 PIT1 X:$00 F1A0 4-20
PIT 2 PIT2 X:$00 F1B0 4-21
DAC 0 DAC0 X:$00 F1C0 4-22
DAC 1 DAC1 X:$00 F1D0 4-23
Comparator A CMPA X:$00 F1E0 4-24
Comparator B CMPB X:$00 F1F0 4-25
QSCI 0 SCI0 X:$00 F200 4-26
QSPI 0 SPI0 X:$00 F220 4-27
I
2
C
I2C X:$00 F280 4-28
FM FM X:$00 F400 4-29
MSCAN CAN X:$00 F800 4-30