Datasheet
56F8036 Data Sheet, Rev. 6
44 Freescale Semiconductor
TMRA2_CMPLD1 $28 Comparator Load Register 1
TMRA2_CMPLD2 $29 Comparator Load Register 2
TMRA2_CSCTRL $2A Comparator Status and Control Register
TMRA2_FILT $2B Input Filter Register
Reserved
TMRA3_COMP1 $30 Compare Register 1
TMRA3_COMP2 $31 Compare Register 2
TMRA3_CAPT $32 Capture Register
TMRA3_LOAD $33 Load Register
TMRA3_HOLD $34 Hold Register
TMRA3_CNTR $35 Counter Register
TMRA3_CTRL $36 Control Register
TMRA3_SCTRL $37 Status and Control Register
TMRA3_CMPLD1 $38 Comparator Load Register 1
TMRA3_CMPLD2 $39 Comparator Load Register 2
TMRA3_CSCTRL $3A Comparator Status and Control Register
TMRA3_FILT $3B Input Filter Register
Reserved
Table 4-8 Analog-to-Digital Converter Registers Address Map
(ADC_BASE = $00 F080)
Register Acronym Address Offset Register Description
ADC_CTRL1 $0 Control Register 1
ADC_CTRL2 $1 Control Register 2
ADC_ZXCTRL $2 Zero Crossing Control Register
ADC_CLIST 1 $3 Channel List Register 1
ADC_CLIST 2 $4 Channel List Register 2
ADC_CLIST 3 $5 Channel List Register 3
ADC_CLIST 4 $6 Channel List Register 4
ADC_SDIS $7 Sample Disable Register
ADC_STAT $8 Status Register
ADC_RDY $9 Conversion Ready Register
ADC_LIMSTAT $A Limit Status Register
ADC_ZXSTAT $B Zero Crossing Status Register
ADC_RSLT0 $C Result Register 0
ADC_RSLT1 $D Result Register 1
Table 4-7 Quad Timer A Registers Address Map (Continued)
(TMRA_BASE = $00 F000)
Register Acronym Address Offset Register Description
