Datasheet

Peripheral Memory-Mapped Registers
56F8036 Data Sheet, Rev. 6
Freescale Semiconductor 45
ADC_RSLT2 $E Result Register 2
ADC_RSLT3 $F Result Register 3
ADC_RSLT4 $10 Result Register 4
ADC_RSLT5 $11 Result Register 5
ADC_RSLT6 $12 Result Register 6
ADC_RSLT7 $13 Result Register 7
ADC_RSLT8 $14 Result Register 8
ADC_RSLT9 $15 Result Register 9
ADC_RSLT10 $16 Result Register 10
ADC_RSLT11 $17 Result Register 11
ADC_RSLT12 $18 Result Register 12
ADC_RSLT13 $19 Result Register 13
ADC_RSLT14 $1A Result Register 14
ADC_RSLT15 $1B Result Register 15
ADC_LOLIM0 $1C Low Limit Register 0
ADC_LOLIM1 $1D Low Limit Register 1
ADC_LOLIM2 $1E Low Limit Register 2
ADC_LOLIM3 $1F Low Limit Register 3
ADC_LOLIM4 $20 Low Limit Register 4
ADC_LOLIM5 $21 Low Limit Register 5
ADC_LOLIM6 $22 Low Limit Register 6
ADC_LOLIM7 $23 Low Limit Register 7
ADC_HILIM0 $24 High Limit Register 0
ADC_HILIM1 $25 High Limit Register 1
ADC_HILIM2 $26 High Limit Register 2
ADC_HILIM3 $27 High Limit Register 3
ADC_HILIM4 $28 High Limit Register 4
ADC_HILIM5 $29 High Limit Register 5
ADC_HILIM6 $2A High Limit Register 6
ADC_HILIM7 $2B High Limit Register 7
ADC_OFFST0 $2C Offset Register 0
ADC_OFFST1 $2D Offset Register 1
ADC_OFFST2 $2E Offset Register 2
ADC_OFFST3 $2F Offset Register 3
ADC_OFFST4 $30 Offset Register 4
ADC_OFFST5 $31 Offset Register 5
Table 4-8 Analog-to-Digital Converter Registers Address Map (Continued)
(ADC_BASE = $00 F080)
Register Acronym Address Offset Register Description