Datasheet

Peripheral Memory-Mapped Registers

56F8036 Data Sheet, Rev. 6

Freescale Semiconductor 47

Table 4-10 Interrupt Control Registers Address Map

(ITCN_BASE = $00 F0E0)

ITCN_IPR0 $0 Interrupt Priority Register 0

ITCN_IPR1 $1 Interrupt Priority Register 1

ITCN_IPR2 $2 Interrupt Priority Register 2

ITCN_IPR3 $3 Interrupt Priority Register 3

ITCN_IPR4 $4 Interrupt Priority Register 4

ITCN_IPR5 $5 Interrupt Priority Register 5

ITCN_IPR6 $6 Interrupt Priority Register 6

ITCN_VBA $7 Vector Base Address Register

ITCN_FIM0 $8 Fast Interrupt Match 0 Register

ITCN_FIVAL0 $9 Fast Interrupt Vector Address Low 0 Register

ITCN_FIVAH0 $A Fast Interrupt Vector Address High 0 Register

ITCN_FIM1 $B Fast Interrupt Match 1 Register

ITCN_FIVAL1 $C Fast Interrupt Vector Address Low 1 Register

ITCN_FIVAH1 $D Fast Interrupt Vector Address High 1 Register

ITCN_IRQP0 $E IRQ Pending Register 0

ITCN_IRQP1 $F IRQ Pending Register 1

ITCN_IRQP2 $10 IRQ Pending Register 2

ITCN_IRQP3 $11 IRQ Pending Register 3

Reserved

ITCN_ICTRL $16 Interrupt Control Register

Reserved

Table 4-11 SIM Registers Address Map

(SIM_BASE = $00 F100)

SIM_CTRL $0 Control Register

SIM_RSTAT $1 Reset Status Register

SIM_SWC0 $2 Software Control Register 0

SIM_SWC1 $3 Software Control Register 1

SIM_SWC2 $4 Software Control Register 2

SIM_SWC3 $5 Software Control Register 3

SIM_MSHID $6 Most Significant Half JTAG ID

SIM_LSHID $7 Least Significant Half JTAG ID

SIM_PWR $8 Power Control Register