Datasheet

56F8036 Data Sheet, Rev. 6

48 Freescale Semiconductor

Reserved

SIM_CLKOUT $A Clock Out Select Register

SIM_PCR $B Peripheral Clock Rate Register

SIM_PCE0 $C Peripheral Clock Enable Register 0

SIM_PCE1 $D Peripheral Clock Enable Register 1

SIM_SD0 $E Peripheral STOP Disable Register 0

SIM_SD1 $F Peripheral STOP Disable Register 1

SIM_IOSAHI $10 I/O Short Address Location High Register

SIM_IOSALO $11 I/O Short Address Location Low Register

SIM_PROT $12 Protection Register

SIM_GPSA0 $13 GPIO Peripheral Select Register 0 for GPIOA

SIM_GPSA1 $14 GPIO Peripheral Select Register 1 for GPIOA

SIM_GPSB0 $15 GPIO Peripheral Select Register 0 for GPIOB

SIM_GPSB1 $16 GPIO Peripheral Select Register 1 for GPIOB

SIM_GPSCD $17 GPIO Peripheral Select Register for GPIOC and GPIOD

SIM_IPS0 $18 Internal Peripheral Source Select Register 0 for PWM

SIM_IPS1 $19 Internal Peripheral Source Select Register 1 for DACs

SIM_IPS2 $1A Internal Peripheral Source Select Register 2 for TMRA

Reserved

Table 4-12 Computer Operating Properly Registers Address Map

(COP_BASE = $00 F120)

COP_CTRL $0 Control Register

COP_TOUT $1 Time-Out Register

COP_CNTR $2 Counter Register

Table 4-13 Clock Generation Module Registers Address Map

(OCCS_BASE = $00 F130)

OCCS_CTRL $0 Control Register

OCCS_DIVBY $1 Divide-By Register

OCCS_STAT $2 Status Register

Reserved

OCCS_OCTRL $5 Oscillator Control Register

OCCS_CLKCHK $6 Clock Check Register

OCCS_PROT $7 Protection Register

Table 4-11 SIM Registers Address Map (Continued)

(SIM_BASE = $00 F100)